<pie_> you people are just too cool
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<carl0s> pointfree, thanks for the video and presentation slides!
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<pie_> pointfree, interesting, what is this thing?
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<azonenberg> pie_: its basically a mask programmed FPGA
<azonenberg> vias are smaller and use less power than SRAM cells, so you get higher logic density and better power efficiency
<azonenberg> you can replace SRAM + pass transistor with via/no-via
<azonenberg> They create a mask set that's common for all of the parts, then you program one via layer to get the target functionality
<azonenberg> so you pay for one mask instead of 20+
<azonenberg> and get a fraction of the NRE of an ASIC, and faster design closure since most of the fun work like transceiver IP etc is done for you
<azonenberg> For prototype runs they probably do e-beam litho, for higher volume probably they spin one mask
<azonenberg> then the "easicopy" line is a full custom standard cell implementation of the same design
<azonenberg> probably using the same ram and transceiver IP etc
<azonenberg> but replacing the ROM-programmed LUTs with raw cell logic
<azonenberg> "FPGAs from Vendor-A or Vendor-X" loool
<cr1901_modern1> PFFFFT
<cr1901_modern1> Where's Vendor-L or Vendor-M?
<pie_> azonenberg, vias?
<pie_> you cant be talking about the stuff on pcbs
<pie_> oh or is this in silicon?
<pie_> that would make more sense
<pie_> though a lot of what you said is still a bit hazy. ah to be a layman :P