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pie_>
you people are just too cool
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carl0s>
pointfree, thanks for the video and presentation slides!
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pie_>
pointfree, interesting, what is this thing?
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azonenberg>
pie_: its basically a mask programmed FPGA
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azonenberg>
vias are smaller and use less power than SRAM cells, so you get higher logic density and better power efficiency
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azonenberg>
you can replace SRAM + pass transistor with via/no-via
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azonenberg>
They create a mask set that's common for all of the parts, then you program one via layer to get the target functionality
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azonenberg>
so you pay for one mask instead of 20+
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azonenberg>
and get a fraction of the NRE of an ASIC, and faster design closure since most of the fun work like transceiver IP etc is done for you
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azonenberg>
For prototype runs they probably do e-beam litho, for higher volume probably they spin one mask
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azonenberg>
then the "easicopy" line is a full custom standard cell implementation of the same design
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azonenberg>
probably using the same ram and transceiver IP etc
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azonenberg>
but replacing the ROM-programmed LUTs with raw cell logic
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azonenberg>
"FPGAs from Vendor-A or Vendor-X" loool
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cr1901_modern1>
PFFFFT
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cr1901_modern1>
Where's Vendor-L or Vendor-M?
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pie_>
azonenberg, vias?
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pie_>
you cant be talking about the stuff on pcbs
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pie_>
oh or is this in silicon?
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pie_>
that would make more sense
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pie_>
though a lot of what you said is still a bit hazy. ah to be a layman :P