02:54 <rqou> woot my UPS (power supply) is finally here after the UPS (shipping company) had difficulty finding the apartment ;P

02:55 <azonenberg> lol

02:55 <rqou> this happens regularly btw

02:55 <azonenberg> you want fun, try telling someone your UPS is coming by fedex

02:55 <azonenberg> :p

08:05 <carl0s> Hi azonenberg, around? Just saw the REcon2015 talk and tried to take a look of the libcrowbar proyect but got a 404 error, also checked on your github and couldn't find it. Also i would like to know if fcplan is open source, would like to do a similar for the PSoC UDBs someday :).

08:41 <azonenberg> lol it would help if he had stayed around more than 30 seconds

09:31 <Lord_Nightmare> libcrowbar?

09:31 <Lord_Nightmare> i see this: https://github.com/npcardoso/PhDThesis/tree/master/libcrowbar/diagnostic-native

09:31 <azonenberg> totally unrelated

09:32 <azonenberg> Lord_Nightmare: That's the coolrunner-2 back end for my previous FPGA toolchain RE

09:32 <azonenberg> pre-greenpak

09:32 <azonenberg> I never formally released it as it was pretty messy code, wanted to clean it up a bunch

09:32 <azonenberg> plan is to merge it into the openfpga repo at some point

09:32 <azonenberg> probably after a full rewrite using the greenpak P&R

09:32 <azonenberg> since this is way better than the pnr i wrote for coolrunner

22:12 <carl0s> azonenberg, sorry about earlier, didn't saw the hour and ran to get some sleep lol

22:14 <carl0s> will wait to see that proyect merged into openfpga repo then, decaping ICs seems very interesting

22:21 <azonenberg> carl0s: (01:31:17) Lord_Nightmare: libcrowbar?

22:21 <azonenberg> (01:31:47) Lord_Nightmare: i see this: https://github.com/npcardoso/PhDThesis/tree/master/libcrowbar/diagnostic-native

22:21 <azonenberg> (01:32:06) azonenberg: Lord_Nightmare: That's the coolrunner-2 back end for my previous FPGA toolchain RE

22:21 <azonenberg> (01:31:54) azonenberg: totally unrelated

22:21 <azonenberg> (01:32:09) azonenberg: pre-greenpak

22:21 <azonenberg> (01:32:43) azonenberg: probably after a full rewrite using the greenpak P&R

22:21 <azonenberg> (01:32:31) azonenberg: plan is to merge it into the openfpga repo at some point

22:21 <azonenberg> (01:32:22) azonenberg: I never formally released it as it was pretty messy code, wanted to clean it up a bunch

22:22 <azonenberg> (01:32:52) azonenberg: since this is way better than the pnr i wrote for coolrunner

22:22 <azonenberg> carl0s: The old code is https://github.com/azonenberg/antikernel/tree/master/legacy-trunk/src/crowbar

22:22 <azonenberg> it needs a near-complete rewrite before i can merge it

22:23 <azonenberg> there's a lot of hard-coded stuff that i now understand the chip well enough to derive from first principles

22:24 <carl0s> bookmarked :), also will take a look into fcplan

22:24 <azonenberg> fcplan is in the same dir

22:24 <azonenberg> It does not belong in the antikernel repo and will get moved

22:24 <azonenberg> this is basically a raw export to github of my internal svn

22:25 <azonenberg> hence the "legacy-trunk" subdirectory :p

22:25 <balrog> azonenberg: I'd probably rename the repo to "antikernel-archive" or something like that and start with a fresh import of only src/doc

22:25 <balrog> because the legacy stuff will now live forever in repo history and take up space :p

22:26 <azonenberg> its not that big

22:27 <carl0s> understood, anyways i will start to poke around the source code from both libcrowbar and fcplan

22:27 <azonenberg> balrog: i didnt import full history

22:27 <azonenberg> just a raw dump of the contents

22:27 <azonenberg> carl0s: yeah you can browse

22:27 <balrog> azonenberg: ah...

22:27 <azonenberg> carl0s: right now the big not-fully-understood bits are the macrocells and clocking

22:27 <azonenberg> i tabled things because at the time, yosys could not synthesize to PLAs

22:28 <azonenberg> so not having a synth tool it was hard to test

22:28 <azonenberg> now that it works that will be my next target

22:28 <azonenberg> Right now my roadmap re openfpga is...

22:28 <azonenberg> #1: finish full support for the slg4662x

22:28 <azonenberg> #2: finish full support for the slg46140

22:28 <azonenberg> #3: libcrowbar port, get basic combinatorial-only support for the xc2c32a in openfpga

22:29 <azonenberg> #4: reverse remaining macrocell logic, get fcplan moved over

22:29 <azonenberg> #5: expanded device support for things like larger coolrunner-2 devices and greenpak5

22:29 <azonenberg> this is in parallel with what other people here are doing on PSoC and such

22:30 <azonenberg> cyrozap and pointfree are the main psoc crew

22:30 <azonenberg> then we have a couple folks looking at older altera stuff

22:30 <azonenberg> whitequark is helping me with greenpak stuff especially usb re on the devkit etc

22:30 <azonenberg> digshadow-s did all of the wet lab work for decapping and imaging the coolrunner dies, I did the microscopy and circuit analysis

22:31 <wpwrak> azonenberg: and gp5 ? :)

22:32 <carl0s> seems like a year or two to get the PSoC project ready, i'm really anxious about that one :D

22:40 <azonenberg> wpwrak: greenpak5 is on the roadmap (see #5 above)

23:02 <wpwrak> aah, wonderful :)

23:04 <azonenberg> But full support for 4 is my higher priority

23:04 <azonenberg> and then merging the existing coolrunner stuff plus making a yosys front end

23:16 <azonenberg> loool ok this was a fun bug

23:17 <azonenberg> so i forked a child process that closed stdin/out because i didnt need them

23:17 <azonenberg> but somewhere in that code there was a log print that wrote to stdout

23:18 <azonenberg> problem is, that code had also opened some sockets

23:18 <azonenberg> and one of those sockets got STDOUT_FILENO as the ID...

23:18 <azonenberg> so the log message got thrown in the middle of my packet :p

23:19 <pie_> oh god haha

23:19 <azonenberg> i'm gonna change it to explicitly redir std* to /dev/null

23:19 <azonenberg> keeping those handles reserved :p

23:57 <pointfree> I had my PSoC gelForth talk at Forth Day. It was a lot of fun. https://www.reddit.com/r/Forth/comments/5eda2n/i_did_my_forth_day_talk_on_saturday_gelforth_a/

23:57 <pointfree> Possibly ignore my comment about presenting logic minimization in two months because I found a paper on non-Quine-McCluskey logic minimization in which can sometimes find prime implicants faster than Quine-McCluskey and supports incremental/partially specified logic minimization. That will take more time to understand than the aforementioned parallel Quine-McCluskey.