sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub92> [artiq] sbourdeauducq commented on issue #866: Well the package is there:... https://github.com/m-labs/artiq/issues/866#issuecomment-351245491
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<sb0> whitequark, ping
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<GitHub117> [artiq] sbourdeauducq commented on issue #847: > M[2:0] settings?... https://github.com/m-labs/artiq/issues/847#issuecomment-351263000
<GitHub37> [artiq] sbourdeauducq commented on issue #847: Er, no all at 1 (but still incorrect) the switches are enabling pull-downs.... https://github.com/m-labs/artiq/issues/847#issuecomment-351264398
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<GitHub59> [artiq] sbourdeauducq commented on issue #856: Sometimes the initialization fails in a loop and this is resolved by reloading the RTM FPGA:... https://github.com/m-labs/artiq/issues/856#issuecomment-351280702
<GitHub177> [artiq] sbourdeauducq commented on issue #856: Sometimes the initialization fails in a loop and this is resolved by reloading the RTM FPGA:... https://github.com/m-labs/artiq/issues/856#issuecomment-351280702
<sb0> rohitksingh_work, hi
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<rohitksingh_work> sb0: hi!
<sb0> rohitksingh_work, how's the mor1kx work coming along?
<rohitksingh_work> sb0: It was going good till Friday, but I haven't got time to work on it since then. I'll get it done this weekend and put up the initial code for review
<sb0> whitequark, does the runtime *always* print something at the warn logging level when there is an incoming Ethernet packet with a broken CRC or a broken preamble?
<sb0> when an ethernet packet arrives, are there only two alternatives: 1) the packet is processed by the stack 2) a warning is printed
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<whitequark> sb0: pong
<whitequark> moment
<whitequark> yes, that is correct
<whitequark> except we no longer check for broken preamble
<GitHub84> [artiq] whitequark commented on issue #866: We only have 0.10.0dev for 32-bit Windows. https://github.com/m-labs/artiq/issues/866#issuecomment-351296794
<whitequark> bb-m-labs: force build --props=package=llvmlite-artiq conda-win32
<bb-m-labs> build #176 forced
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #176 of conda-win32 is complete: Failure [failed conda_clean] Build details are at http://buildbot.m-labs.hk/builders/conda-win32/builds/176
<whitequark> ImportError: cannot import name '_remove_dead_weakref'
<whitequark> WTF
<sb0> oh that was win32
<sb0> yeah conda python 3.5 is broken for win32.
<whitequark> broken in general?
<whitequark> or just on our buildsystem?
<GitHub155> [artiq] sbourdeauducq commented on issue #866: Is that 32-bit Windows? Conda + win32 + python3.5 is broken. Reintroducing win32 needs #652. https://github.com/m-labs/artiq/issues/866#issuecomment-351298294
<sb0> broken in general
<whitequark> amazing
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<GitHub164> [misoc] sbourdeauducq pushed 3 new commits to master: https://github.com/m-labs/misoc/compare/2ee3d5496c54...23a173e68364
<GitHub164> misoc/master 907d6df Sebastien Bourdeauducq: liteeth/1000basex: add full PCS/PMA with transceiver interface (untested)
<GitHub164> misoc/master 75ad039 Sebastien Bourdeauducq: targets/kasli: integrate 1000BASE-X PCS/PMA
<GitHub164> misoc/master 23a173e Sebastien Bourdeauducq: liteeth/1000basex: fix compilation errors
<bb-m-labs> build #294 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/294
<GitHub6> [misoc] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/misoc/commit/ab4034191f852e411ed16777f9f6263a1ae2c7b6
<GitHub6> misoc/master ab40341 Sebastien Bourdeauducq: liteeth/1000basex: MMCM has fractional divide on output 0 only
<bb-m-labs> build #295 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/295
<sb0> ERROR: [Place 30-847] GT-CHANNEL instance GTPE2_CHANNEL drives 2 loads of type MMCME2_ADV. This is an unplaceable situation since all t
<sb0> hese loads must be placed in a single clock region but each clock region has a maximum of 1 such sites.
<sb0> fucking xilinx garbage
<sb0> first they design their trash with maximally obtrusive frequency output requirements, then they don't let you fix it
<sb0> of course their shitware spits out this warning late into the compilation for maximum time-wasting, as usual
<sb0> if their junk won't behave when inserting bufg/r/h, I wonder if the oversampling trick can be used for TX but not RX
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<sb0> hm tx and rx have independent clock dividers, so unless xilinx made up more rules to fuck things up, it may be possible
<rjo> sb0: then are all three sayma-amcs M[2:0] switches set now?
<sb0> rjo, not yet, will go to the lab after getting vivado to behave with the gtp and do that
<rjo> sb0: ack. thanks!
<sb0> rjo, technosystem should have kasli's soon. are you keeping tabs on that? where should they go?
<GitHub31> [misoc] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/misoc/compare/ab4034191f85...923b63f7b131
<GitHub31> misoc/master 923b63f Sebastien Bourdeauducq: liteeth/1000basex: MMCME2 expects CLKIN period in nanoseconds
<GitHub31> misoc/master c7d4cba Sebastien Bourdeauducq: liteeth/1000basex: spray BUFGs everywhere to avoid dealing with arcane Xilinx clock routing rules
<sb0> rjo, okay, it compiles now, will fix the M switches in 20-30min
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<bb-m-labs> build #296 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/296
<rjo> sb0: i am. they will go here.
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<GitHub69> [smoltcp] phil-opp commented on issue #75: @whitequark Is there anything I should improve to get this PR merged? https://github.com/m-labs/smoltcp/pull/75#issuecomment-351349076
<GitHub157> [artiq] enjoy-digital commented on issue #856: Thanks. I look at that today. https://github.com/m-labs/artiq/issues/856#issuecomment-351363045
<rjo> ashafir: this is the urukul testing issue: https://github.com/m-labs/sinara/issues/354
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<GitHub38> [smoltcp] phil-opp opened pull request #94: Add a PacketFilter trait to abstract over concrete SocketSet type (master...packet_filter) https://github.com/m-labs/smoltcp/pull/94
<GitHub7> [smoltcp] dlrobertson commented on pull request #75 83a42eb: No validation of the write buffers length here either. https://github.com/m-labs/smoltcp/pull/75#discussion_r156651297
<GitHub36> [smoltcp] dlrobertson commented on pull request #75 83a42eb: Same here. If we're writing to a short buffer, this could be out of bounds. https://github.com/m-labs/smoltcp/pull/75#discussion_r156649906
<GitHub100> [smoltcp] dlrobertson commented on pull request #75 83a42eb: We also need to verify that the length of `data` is 4 right? In theory `length` could be 4, but `data.len()` could be something else right? https://github.com/m-labs/smoltcp/pull/75#discussion_r156650888
<GitHub37> [smoltcp] dlrobertson commented on pull request #75 83a42eb: The length of the packet has not been checked before this point right? This could be out of bounds right? https://github.com/m-labs/smoltcp/pull/75#discussion_r156649605
<sb0> so we have the non-opticlock urukul working first? hmm
<sb0> rjo, what is flashed in sayma1?
<sb0> oh, misoc
<sb0> cool, so yes it boots!
<GitHub87> [artiq] sbourdeauducq commented on issue #847: After setting the switches into that position, the board boots from the bitstream that @jordens flashed, but not the one I built from master and flashed with artiq_flash. https://github.com/m-labs/artiq/issues/847#issuecomment-351389604
<GitHub145> [artiq] sbourdeauducq commented on issue #847: After setting the switches into that position, the board boots from the bitstream that @jordens had flashed earlier today, but not the one I built from master and flashed with artiq_flash. https://github.com/m-labs/artiq/issues/847#issuecomment-351389604
<GitHub116> [artiq] jordens pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/3cf5cef16866...a9d0f253a5b8
<GitHub116> artiq/master 2917208 Robert Jordens: artiq_flash: fix sayma flashing...
<GitHub116> artiq/master a9d0f25 Robert Jordens: sayma_amc: set bitstream and config parameters...
<rjo> sb0: ack. that was artiq with --integrated rom with the patches as of now.
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<sb0> rjo, it works with just the artiq_flash fixes
<rjo> sb0: ok then we can back out the spi width and config rate changes. the rest is still needed.
<rjo> well. i didn't even everify them. just that copied from greg...
<rjo> let me do that.
<rjo> checked CFGBVS and CONFIG_VOLTAGE.
<rjo> sb0: so you are saying it boots with a bitstream that you compiled with the artiq from yesterday and the artiq_flash from now?
<sb0> yes
<rjo> then i'll kill the CONFIGRATE and SPI_BUSWIDTH lines.
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<GitHub110> [artiq] jordens pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/5e251cd85c90b980448894ab91ea968b81c3b709
<GitHub110> artiq/master 5e251cd Robert Jordens: sayma_amc: remove redundant bitstream options...
<sb0> we may still want 1-bit SPI to load the RTM FPGA, depending which route is chosen
<rjo> sb0: you haven't tested bios in flash or runtime in flash yet, right?
<rjo> sb0: yes. but that doesn't work with the current broken slave serial wiring. we still need to implement that separately.
<GitHub36> [artiq] jordens commented on issue #847: 2917208d https://github.com/m-labs/artiq/issues/847#issuecomment-351394440
<GitHub67> [artiq] jordens closed issue #847: Sayma won't boot from flash https://github.com/m-labs/artiq/issues/847
<sb0> rjo, I have tested it, it doesn't work, the spiflash core always read 0xfff.....
<sb0> there is another issue open about that
<rjo> sb0: yes.
<rjo> sb0: did you ever try with a reduced divider?
<sb0> I changed the divider a bit yes, no change
<rjo> it's annoying that integrated-rom completely disables the flash...
<sb0> oh I have a patch for that
<sb0> let me forward it to you
<sb0> maybe there is something going on with the STARTUPE3 ...
<rjo> sb0: ack.
<bb-m-labs> build #946 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/946
<bb-m-labs> build #618 of artiq-win64-test is complete: Warnings [warnings python_coverage] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/618 blamelist: Robert Jordens <jordens@gmail.com>
<bb-m-labs> build #1830 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1830
<GitHub57> [smoltcp] phil-opp commented on pull request #75 83a42eb: Thanks for the review! I'm a bit confused, since my original PR had such a check. It was called a "useless check" [in the previous review](https://github.com/m-labs/smoltcp/pull/75#discussion_r153168767), so I removed it. Should I add it again? https://github.com/m-labs/smoltcp/pull/75#discussion_r156672259
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<bb-m-labs> build #947 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/947
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<GitHub189> [smoltcp] dlrobertson commented on pull request #75 83a42eb: When in doubt go with what @whitequark says. I am curious as to why that check is useless though. I would think the following would cause an out of bounds access, but I could be mistaken.... https://github.com/m-labs/smoltcp/pull/75#discussion_r156674048
<bb-m-labs> build #619 of artiq-win64-test is complete: Warnings [warnings python_coverage] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/619 blamelist: Robert Jordens <rj@m-labs.hk>
<bb-m-labs> build #1831 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1831
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<rjo> i'll reboot the saymas. (this should also need locking)
<rjo> sb0: 0x70000000 (from your patch) is occupied. and the runtime does not compile. and it refuses to --no-compile-software b/c no bios...
<rjo> let's do without the csr interface for now.
<GitHub78> [smoltcp] whitequark commented on pull request #94 613454f: As above. https://github.com/m-labs/smoltcp/pull/94#discussion_r156754057
<GitHub139> [smoltcp] whitequark commented on pull request #94 613454f: `filter: &mut F` https://github.com/m-labs/smoltcp/pull/94#discussion_r156753984
<GitHub36> [smoltcp] whitequark commented on pull request #94 613454f: This really should not return an `EthernetPacket`. We may not even be running over Ethernet! https://github.com/m-labs/smoltcp/pull/94#discussion_r156754547
<GitHub12> [smoltcp] whitequark commented on pull request #94 613454f: As above. https://github.com/m-labs/smoltcp/pull/94#discussion_r156754185
<GitHub22> [smoltcp] whitequark commented on pull request #94 613454f: This too. https://github.com/m-labs/smoltcp/pull/94#discussion_r156754849
<GitHub77> [smoltcp] whitequark commented on pull request #94 613454f: As above. https://github.com/m-labs/smoltcp/pull/94#discussion_r156754039
<GitHub155> [smoltcp] whitequark commented on pull request #94 613454f: As above. https://github.com/m-labs/smoltcp/pull/94#discussion_r156754166
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<GitHub48> [misoc] jordens pushed 1 new commit to master: https://github.com/m-labs/misoc/commit/a1a58f62e5a236ecc2747d8d02342cea951a04bd
<GitHub48> misoc/master a1a58f6 Robert Jordens: sayma_amc: fix flash boot address, closes #846
<bb-m-labs> build #297 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/297
<GitHub118> [artiq] philipkent commented on issue #866: Hi.... https://github.com/m-labs/artiq/issues/866#issuecomment-351515857
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<GitHub5> [artiq] whitequark commented on issue #866: Are you perhaps missing the conda-forge channel? https://github.com/m-labs/artiq/issues/866#issuecomment-351517045
<GitHub59> [artiq] philipkent commented on issue #866: It was missing the conda-forge channel. That fixed it. https://github.com/m-labs/artiq/issues/866#issuecomment-351529203
<GitHub125> [artiq] jordens closed issue #866: Installing Artiq 3.1 from Conda channel https://github.com/m-labs/artiq/issues/866
<GitHub93> [artiq] hartytp opened issue #867: Developer documentation https://github.com/m-labs/artiq/issues/867
<GitHub140> [artiq] jbqubit commented on issue #867: I agree. The level of documentation of misoc and migen was a hurdle when Arpit was working on a hardware driver for Zotino. Some ad hoc breadcrumb trails I found helpful including the following. ... https://github.com/m-labs/artiq/issues/867#issuecomment-351548062
<GitHub4> [artiq] jbqubit commented on issue #854: @sbourdeauducq Any luck with this using external JTAG? https://github.com/m-labs/artiq/issues/854#issuecomment-351549381
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<GitHub115> [artiq] jbqubit opened issue #868: .bit build, file location expected by artiq_flash https://github.com/m-labs/artiq/issues/868
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<GitHub133> [artiq] jbqubit opened issue #869: artiq_flash support for Sayma_RTM https://github.com/m-labs/artiq/issues/869
<GitHub93> [artiq] jbqubit commented on issue #847: Confirmed that I can flash using ```artiq_flash -t sayma```. Thank you @jordens ! https://github.com/m-labs/artiq/issues/847#issuecomment-351559669
<GitHub139> [artiq] jbqubit opened issue #870: Sayma: no debug info on flterm https://github.com/m-labs/artiq/issues/870
<GitHub97> [artiq] sbourdeauducq commented on issue #867: > Short (often single-letter) function and variable names... https://github.com/m-labs/artiq/issues/867#issuecomment-351563359
<mithro> Last chance to sign up for FPGA Miniconf before I email everyone about it -> https://linux.conf.au/programme/miniconfs/fpga/
<GitHub90> [artiq] sbourdeauducq commented on issue #868: artiq-flash is meant to be used in conjunction with the conda packages, not source builds (unless you reorganize files like the conda script does). https://github.com/m-labs/artiq/issues/868#issuecomment-351563979
<GitHub37> [artiq] sbourdeauducq commented on issue #870: Is the done led on? Did you set up the M switches? https://github.com/m-labs/artiq/issues/870#issuecomment-351564156
<sb0> rjo, I was using that patch with bare misoc without artiq