<GitHub30>
[artiq] enjoy-digital commented on issue #861: @sbourdeauducq: i'm pretty sure all was fine with kcu105 + ad9154 fmc and also with my sayma_test design. I need to do more tests but a quick check of the generated clocks would be interesting. https://github.com/m-labs/artiq/issues/861#issuecomment-348913000
<_florent_>
sb0: not sure i did the test with RXSLIDEMODE=PMA on Ultrascale
<sb0>
_florent_, I remember seeing something in the doc that said the same as K7
<sb0>
doesn't work in buffer bypass mode and txoutclk phase is unclear
<sb0>
*rxoutclk
<_florent_>
sb0: have you seen serwb initialization issues recently?
<sb0>
I haven't touched the board again for the last days
<_florent_>
ok i'll do some tests on the boards for that point
<_florent_>
sb0: for scrambling on serwb, what was the code you were suggesting to reuse?
<sb0>
_florent_, in drtio link layer. look at the older versions before I added the more complex shared-state K+D scrambler
<sb0>
unless you want this shared state too
<_florent_>
ok
<_florent_>
don't know, you are the one deciding :)
<_florent_>
i'll look at that and see
<sb0>
I haven't looked at the details of the serwb protocol, but the idea of sharing the K+D state is that you can synch the scrambler on Ks and it is immediately ready to process Ds
<_florent_>
ok thanks, i'll implement the scrambler before doing more tests on initialization.
<sb0>
that scrambler is actually a pretty low-priority item, we can demonstrate the boards without it...
<sb0>
right now the major source of pain is rgmii
<sb0>
let me ping greg
<_florent_>
sb0: yes i know, i'm ok to do some test on rgmii, but just want to be sure i'm not wasting time on a phy config or something like that.
<_florent_>
sb0: I'm focusing on initialization issues, then additionnal features
<sb0>
ok
<GitHub35>
[migen] sbourdeauducq pushed 1 new commit to master: https://git.io/vb3ZK
<GitHub35>
migen/master e63093b N. Engelhardt: genlib/fifo: fix data output changing while not reading when fifo is full in non-fwft mode