sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<cr1901_modern>
sb0: When you did REing for the Ikos Pegasus did you get as far as extracting the XC2xxx (I think they were) bitstreams?
<rqou>
not sure what the context is, but XC2 bitstream parsing for RE purposes is actually done, just undocumented
<cr1901_modern>
Where? (And I was mistaken they were xc4xxx)
<cr1901_modern>
Or I mean who did it? Are you referring to digshadow's comments in ##openfpga?
<rqou>
xc2jed2json plus appropriate use of yosys "techmap"
<rqou>
this is for xc2 only, not 4000/9500
<cr1901_modern>
rqou: Apparently xc2c32 is a coolrunner part?
<rqou>
yes
<cr1901_modern>
I meant "xc2064"/"xc2016" which are the first FPGAs Xilinx produced
<cr1901_modern>
I was not aware that Xilinx reused "xc2" for Coolrunner
<rqou>
no those aren't the same thing
<cr1901_modern>
I noticed you combined 4000/9500. Are they also CPLDs
<cr1901_modern>
?*
<cr1901_modern>
well 9500 certainly is, but xc4000?
<rqou>
no, 4000 is an fpga
<cr1901_modern>
Ahh okay then. So the context is that IKOS Pegasus is an ASIC emulator that you'll occassionally see pictures of on Wikimedia. I found out in the past, sb0 did RE work on it,
<cr1901_modern>
and right now it's sitting in storage at Electrolab in France
<cr1901_modern>
I was wondering if the RE work got as far as REing what was already stored on the FPGAs/bitstream format
<sb0>
I suppose you'd load your asic design in there...
<cr1901_modern>
I thought some of them were used for control purposes/glue logic
<rqou>
man i really need to spend some time living in Europe :P
<rqou>
all the cool stuff and people seem to be over there
<sb0>
rqou, the artiq boards in hk have more LUTs than this thing
<sb0>
faster too
<rqou>
yes of course
<rqou>
but it's always cool to see hardware that _looks_ really fancy and expensive
<rqou>
hmm, i suppose m-labs meets that criteria too :P
<cr1901_modern>
more chips == more impressive (perceptually anyway)
<GitHub81>
[smoltcp] dlrobertson commented on pull request #98 bcbdef3: After looking at the tests, I'm not sure how a set of mock IP addresses would work. So I added the `ipv4` specific stuff in a `ipv4_locals` module. Would it be an public mock `IpAddress` be an `IPv6` variant if `proto-ipv6` was enabled and `IPv4` if not? Or would we have a public collection of mock IPv4 addresses and a public collection of IPv6 addresses
<GitHub177>
[smoltcp] dlrobertson commented on pull request #98 bcbdef3: After looking at the tests, I'm not sure how a set of mock IP addresses would work. So I added the `ipv4` specific stuff in a `ipv4_locals` module. Would the public mock `IpAddress` be an `IPv6` variant if `proto-ipv6` was enabled and `IPv4` if not? Or would we have a public collection of mock IPv4 addresses and a public collection of IPv6 addresses.
<GitHub38>
[smoltcp] BurntPizza opened pull request #100: Add faster TCP checksum implementation for x86_64 (master...master) https://github.com/m-labs/smoltcp/pull/100
<GitHub156>
[artiq] gkasprow commented on issue #854: @sbourdeauducq This is regular MII mode. The PHY is operating in 1Gbit mode and converting to 100Mbit mode. We use home-made sata-sfp cables for long time in CBM experiment. In which place your cable breaks? https://github.com/m-labs/artiq/issues/854#issuecomment-353717400
<GitHub30>
[artiq] sbourdeauducq commented on issue #854: Again, the cable you gave me 1) had its solders inside the SFP broken 2) causes issues with at least one of my media converters due to missing EEPROM and/or link indicator signal. I had to make new cables using copper SFP-SFP cables cut in half and soldered to SATA connectors, but that's still fragile.... https://github.com/m-labs/artiq/issues/854#issuecomment-3537184
<GitHub148>
[artiq] sbourdeauducq commented on issue #854: Again, the cable you gave me 1) had its solders inside the SFP broken 2) causes issues with at least one of my media converters due to missing EEPROM and/or link indicator signal. I had to make new cables using copper SFP-SFP cables cut in half and soldered to SATA connectors, but that's still fragile.... https://github.com/m-labs/artiq/issues/854#issuecomment-35371
<GitHub39>
[artiq] sbourdeauducq commented on issue #854: Again, the cable you gave me 1) had its solders inside the SFP broken 2) causes issues with at least one of my media converters due to missing EEPROM and/or link indicator signal. I had to make new cables using copper SFP-SFP cables cut in half and soldered to SATA connectors, but that's still fragile.... https://github.com/m-labs/artiq/issues/854#issuecomment-3537184
<GitHub52>
[artiq] sbourdeauducq commented on issue #854: Yes, I power-cycled it. The FPGA power doesn't come back until the JTAG probe is unplugged anyway, and sometimes it also needs some fiddling with the USB connector due to some other bugs. https://github.com/m-labs/artiq/issues/854#issuecomment-353719299
<GitHub195>
[artiq] sbourdeauducq commented on issue #854: Can you get two media converters to work with the MII firmware, send us one (with the corresponding tested SATA/SFP cable), and keep the other for testing ARTIQ on your side? https://github.com/m-labs/artiq/issues/854#issuecomment-353719651
<sb0>
what happens if the gth transceiver clock is not applied during the first initialization attempt? is there some miracle that makes it well-behaved and waits for the clock to be there? does it self-destruct like the altera trash does?
<_florent_>
sb0: what are you testing, between what and what?
<sb0>
_florent_, sayma to sayma, connected via sfp, and the code in artiq master
<_florent_>
sb0: with one sfp or 2? what's the behavious?
<_florent_>
behaviour
<sb0>
one SFP
<sb0>
receiver does not detect link (board::csr::DRTIO[0].link_status_read stays at 0)
<sb0>
I don't know if it transmits or not, nor if the CPLL is locking. note that with the ARTIQ DRTIO design, the transceiver clocks are not present when the FPGA is configured, since this needs si5324 setup
<sb0>
for both master and satellite
<sb0>
the GTX seemed fine with that, but maybe the GTH is not
<_florent_>
sb0: from the test i did, i think it's also fine on GTH
<_florent_>
sb0: when testing jesd, i remember having no clock on GTH refclk at startup, then was configuring the rtm clocking and GTH were operationals
<cr1901_modern>
sb0: Are misoc wishbone peripherals still limited to 256MB of contiguous allocation? I seem to recall that this limitation was removed, but can't remember.
<GitHub114>
[artiq] a-shafir commented on issue #860: There is a visible on a scope trailing (extra) short pulse on SCK. With a simple shift register as in CPLD it makes all received bits shifted etc. Probably not all SPI IC are sensitive to it because some of them have "de-glitching" filter. CPLD certainly need a very clean clock. HMC830 possible too. ... https://github.com/m-labs/artiq/issues/860#issuecomment-353738408
<GitHub88>
[smoltcp] BurntPizza commented on issue #100: I've revised to hopefully improve further upon 275eb90785a26ed1bd942f087c2d81647dc58f84, which was apparently the one simple formulation which works that I didn't try last night. :\... https://github.com/m-labs/smoltcp/pull/100#issuecomment-353748942