<GitHub171>
[artiq] sbourdeauducq commented on issue #854: I don't have a cable and I'd rather not install the crappy Xilinx drivers. They never work and typically waste a few hours of yak-shaving every time. https://github.com/m-labs/artiq/issues/854#issuecomment-351565507
<GitHub186>
[artiq] sbourdeauducq commented on issue #854: I don't have a cable and I'd rather not install the crappy Xilinx drivers. They never work and typically waste a few hours on yak-shaving every time. https://github.com/m-labs/artiq/issues/854#issuecomment-351565507
<sb0>
anyway I cannot find any sayma flash problem anymore
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<GitHub21>
[artiq] jordens commented on issue #867: A lot of those single letter variables follow just follow signal names that are as old as the flip flop itself. You have to address that critique to the inventors of the flip-flop and everybody else after them. I see no reason to comment that.... https://github.com/m-labs/artiq/issues/867#issuecomment-351624219
<GitHub1>
[artiq] whitequark commented on issue #868: I agree with @jbqubit that the filesystem layout of artiq_flash (which, only by coincidence, is what conda packages use) should match the output of `python -m artiq.gateware.targets.xxx`. This also makes it easier to do things like building everything but the bitstream locally, which unfortunately are also blocked because of similarly poor design decisions in regards to paths
<GitHub184>
[artiq] whitequark commented on issue #868: @sbourdeauducq using absolute paths, assuming that if a script is generated it needs to be run immediately, assuming that a generated file will be run on the same host. I was trying to make it possible to make misoc build process network transparent, but wasted nearly a week of time and gave up in the end, it would require too many changes in misoc. Maybe another time...
<GitHub1>
[artiq] whitequark commented on issue #868: @sbourdeauducq using absolute paths, assuming that if a script is generated it needs to be run immediately, assuming that a generated file will be run on the same host. I was trying to make it possible to make misoc build process network transparent, but wasted nearly a week of time and gave up in the end, it would require too many changes in misoc. Maybe another time......
<GitHub40>
[artiq] sbourdeauducq commented on issue #868: It was never intended to be a network build system. If we start doing complicated things like that, maybe there are existing build systems that can be reused? https://github.com/m-labs/artiq/issues/868#issuecomment-351759964
<GitHub83>
[artiq] whitequark commented on issue #868: There are, but I wanted to hack together something that would mainly just let me test gateware changes without having Xilinx. Actually, maybe it is easier to just give up and install Xilinx junk on my laptop. Is it possible for me to borrow M-Labs' license using their flexlm crap? https://github.com/m-labs/artiq/issues/868#issuecomment-351763293
<GitHub72>
[artiq] jordens commented on issue #868: I'd be fine with packaging the binaries as `gateware/top.bit`, `software/runtime/runtime.fbi`, `software/bios/bios.bin`. The added directories are a minor inconvenience. https://github.com/m-labs/artiq/issues/868#issuecomment-351763976
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<GitHub53>
[migen] sbourdeauducq pushed 1 new commit to master: https://git.io/vbVwO
<GitHub53>
migen/master 8e87a14 Sebastien Bourdeauducq: sayma_rtm: add Allaki control pins
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<GitHub78>
[artiq] gkasprow commented on issue #854: you can buy it on aliexpress, ebay, just 10$ per piece
<davidc__>
sb0: my RGA arrived, though it was packed terribly. Filament seems intact though. I'll take (external) pictures and figure out a pinout later today
<davidc__>
sb0: it'll probably be a few weeks until I have time to machine connectors/adapters for it.
<sb0>
davidc__, just stick pins like Amphenol AT62-16-0122 into it + flying wires (keep the rf ones short and the collector one shielded)
<sb0>
unless you have a competent machinist + lots of equipment on hand, machining sounds like a royal PITA
<sb0>
collector one should be reasonably short as well, otherwise capacitance will reduce your scan speed
<davidc__>
sb0: I'm an (in)competent machinist, and have a lathe and mill sufficient to work SS :)
<GitHub192>
[artiq] jbqubit commented on issue #868: Ok. I can better rephrase what I'm asking for now. I'd like to be able to use ```artiq_flash``` with both conda and locally generated binaries. Perhaps a flag to ```artiq_flash``` could indicate which directory contains the build results. https://github.com/m-labs/artiq/issues/868#issuecomment-351831006
<GitHub177>
[artiq] jbqubit commented on issue #870: I set "M switches" on PCB "HS1" to 1234 -> 0111. I can now flash the board using artiq_flash -t sayma and see on ttyUSB2 MiSoC BIOS messages. Thanks! ... https://github.com/m-labs/artiq/issues/870#issuecomment-351831260
<GitHub140>
[artiq] jordens commented on issue #872: From the symptoms this is the same as the 1.8V supply dying and the same as the FTDI chip locking up when bein accessed (or openocd ctrl-C-ed) when Sayma is not powered. We already have issues for those. ... https://github.com/m-labs/artiq/issues/872#issuecomment-351832606
<GitHub192>
[artiq] gkasprow commented on issue #873: @jbqubit this is correct behaviour. DRT line causes MMC reset. Please disable flow control. Or unsolder pin 3 of T23. I can add a DIP switch that enables USB firmware update... https://github.com/m-labs/artiq/issues/873#issuecomment-351870640
<GitHub174>
[artiq] gkasprow commented on issue #873: @jbqubit this is correct behaviour. Serial port DTR line causes MMC reset. Please disable flow control. Or unsolder pin 3 of T23. I can add a DIP switch that enables USB firmware update... https://github.com/m-labs/artiq/issues/873#issuecomment-351870640