sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> rjo1, what controllers do we include in artiq? asking this re. your out-of-tree newfocus driver
<GitHub33> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/migen/commit/c4d1cd1ca8b9388d0fab339237d8fb2e180a30c1
<GitHub33> migen/master c4d1cd1 William D. Jones: fhdl/tracer: support Python 3.6. Closes #62. (#98)
<bb-m-labs> build #219 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/219
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<sb0> rohitksingh_work, did you test the modified mor1kx core in simulation and on board?
<sb0> have you built and loaded rust programs into its memory?
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<GitHub184> [misoc] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/misoc/commit/123a5d593571135570cb946c307f58ee8d1c7c45
<GitHub184> misoc/master 123a5d5 Sebastien Bourdeauducq: sayma_amc: clean up MII clock constraints
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<bb-m-labs> build #309 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/309
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<GitHub127> [smoltcp] crawford opened issue #97: segment not in receive window in server example https://github.com/m-labs/smoltcp/issues/97
<sb0> _florent_, do we need the QPLL for DRTIO?
<sb0> IMPORTANT:
<sb0> Upon device configuration, the clock output
<sb0> from MGTREFCLK[0/1]P and MGTREF
<sb0> CLK[0/1]N can only be used under the following conditions:
<sb0> from the IBUFDS_GTE3/4 which takes inputs
<sb0> •
<sb0> The GTPOWERGOOD signal has already asserted High.
<sb0> •
<sb0> A minimum delay of 250 μs has passed after GTPOWERGOOD asserts High.
<sb0> everytime i read the manual of this trash I find new pearls....
<sb0> _florent_, anyway it seems we don't need the QPLL?
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<_florent_> sb0: we don't need QPLL for 3gbps linerate
<_florent_> sb0: i validated link with CPPL at 3gbps
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<sb0> _florent_, the clock domains are rtio and rtio_rx. why did you rename rtio to rtio_tx?
<sb0> well not rename everywhere, e.g. not here https://github.com/enjoy-digital/sayma_test/blob/master/gateware/drtio/common.py#L12 but in clockaligner yes
<_florent_> sb0: IIRC rtio and rtio_tx are using the same clock, just that we are generating different resets for rtio_tx
<sb0> hm. do those different resets need to be there? they were not needed for GTX
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<_florent_> sb0: from what i remember it's more related to havint multiple lane. But i'm reworking the init sequence and will see if we can avoid that.
<whitequark> dlrobertson: because the trait was a basic version of a ManagedMap, and we'll need ManagedMap elsewhere
<whitequark> i.e. the trait represented a map, but we needed more fields for a map
<GitHub5> [artiq] whitequark commented on issue #877: @jonaskeller Could you please run flterm to see if there are any messages on the console? This seems like the runtime panicking, and seeing the panic message would be very helpful. https://github.com/m-labs/artiq/issues/877#issuecomment-353300094
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<GitHub124> [artiq] sbourdeauducq commented on issue #877: Do we have backtraces yet? https://github.com/m-labs/artiq/issues/877#issuecomment-353304727
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<GitHub19> [artiq] whitequark commented on issue #877: Not yet. https://github.com/m-labs/artiq/issues/877#issuecomment-353307116
<GitHub144> [smoltcp] whitequark commented on issue #97: Thanks for the report. https://github.com/m-labs/smoltcp/issues/97#issuecomment-353307483
<GitHub51> [smoltcp] whitequark commented on issue #97: This is not actually a bug, but a side effect of the fact that `server.rs` never reads from `tcp:6969`. As a result, the TCP in your kernel is ever trying (unsuccessfully) to push the rest of the data sent by curl in. Since `server.rs` also never aborts the connection (it only closes its half-connection) this can go on indefinitely. There is no off-by-one involved.... h
<GitHub157> [smoltcp] whitequark closed issue #97: segment not in receive window in server example https://github.com/m-labs/smoltcp/issues/97
<GitHub153> [smoltcp] whitequark commented on issue #97: This is not actually a bug, but a side effect of the fact that `server.rs` never reads from `tcp:6969`. As a result, the TCP in your kernel is ever trying (unsuccessfully) to push the rest of the data sent by curl in. Since `server.rs` also never aborts the connection (it only closes its transmit half-connection) this can go on indefinitely. There is no off-by-one involve
<GitHub83> [smoltcp] whitequark pushed 1 new commit to master: https://github.com/m-labs/smoltcp/commit/3347bbe60bb22b83434782985bb61feb6f4c2f0d
<GitHub83> smoltcp/master 3347bbe whitequark: Use a more specific log message for keep-alive or probe TCP packets.
<GitHub144> [smoltcp] whitequark commented on issue #97: I've improved the log message in 3347bbe. https://github.com/m-labs/smoltcp/issues/97#issuecomment-353318580
<travis-ci> m-labs/smoltcp#496 (master - 3347bbe : whitequark): The build passed.
<GitHub87> [artiq] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/701308474fa0...4fbc8772a587
<GitHub87> artiq/master a232512 Sebastien Bourdeauducq: Revert "sayma: set up Si5324 for RGMII clock rerouting"...
<GitHub87> artiq/master 4fbc877 Sebastien Bourdeauducq: sayma: allocate all user LEDs to RTIO, make one TTL SMA input
<bb-m-labs> build #963 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/963
<bb-m-labs> build #633 of artiq-win64-test is complete: Warnings [warnings python_coverage] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/633 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #1845 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1845
<GitHub184> [smoltcp] whitequark pushed 1 new commit to master: https://github.com/m-labs/smoltcp/commit/d1e229261f8de0641e469989e6b03bb162dd2290
<GitHub184> smoltcp/master d1e2292 whitequark: Panic on an attempt of subtracting sequence numbers with underflow....
<GitHub113> [smoltcp] whitequark commented on issue #62: @pothos I'm finally making progress on this—see d1e2292 for one method I'm using to expose underlying bugs. I am afraid that your fix is hiding one of them. https://github.com/m-labs/smoltcp/issues/62#issuecomment-353340310
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<travis-ci> m-labs/smoltcp#497 (master - d1e2292 : whitequark): The build passed.
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<GitHub63> [artiq] jordens opened issue #878: IR generator bug on "" + str(1) https://github.com/m-labs/artiq/issues/878
<GitHub163> [artiq] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/4fbc8772a587...69d7e93e99eb
<GitHub163> artiq/master a6ffe9f Sebastien Bourdeauducq: drtio: add Sayma top-level designs
<GitHub163> artiq/master 69d7e93 Sebastien Bourdeauducq: drtio: adapt examples to Sayma
<sb0> _florent_, no RXSynchronizer?
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<bb-m-labs> build #964 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/964
<GitHub24> [artiq] klickverbot commented on issue #878: More minimal example:... https://github.com/m-labs/artiq/issues/878#issuecomment-353379486
<bb-m-labs> build #634 of artiq-win64-test is complete: Warnings [warnings python_coverage] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/634 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #1846 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1846
<sb0> what is $MISOC_EXTRA_VIVADO_CMDLINE for in the conda build.sh files?
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<GitHub11> [artiq] sbourdeauducq pushed 2 new commits to master: https://github.com/m-labs/artiq/compare/69d7e93e99eb...8adb50037f3c
<GitHub11> artiq/master 6cad942 Sebastien Bourdeauducq: conda: add Sayma RTM package
<GitHub11> artiq/master 8adb500 Sebastien Bourdeauducq: conda: remove superfluous SoC build command line arguments
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<sb0> and is BUILD_SETTINGS_FILE ($HOME/.m-labs/build_settings.sh) used at all?
<sb0> it doesn't exist on the buildbot afaict
<sb0> bb-m-labs, force build --props=package=artiq-sayma_rtm artiq-board
<bb-m-labs> build forced [ETA 13m10s]
<bb-m-labs> I'll give a shout when the build finishes
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<bb-m-labs> build #965 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/965
<sb0> _florent_, hmm maybe this timing failure has to do with the serwb unreliability?
<GitHub190> [artiq] sbourdeauducq commented on issue #856: Also the RTM design doesn't meet timing... https://github.com/m-labs/artiq/issues/856#issuecomment-353390585
<GitHub4> [artiq] sbourdeauducq commented on issue #854: @gkasprow can you send us those firmwares for tomorrow (HKT)? https://github.com/m-labs/artiq/issues/854#issuecomment-353390896
<GitHub114> [artiq] sbourdeauducq opened issue #879: remove BUILD_SETTINGS_FILE from conda scripts? https://github.com/m-labs/artiq/issues/879
<bb-m-labs> build #966 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/966
<bb-m-labs> build #635 of artiq-win64-test is complete: Warnings [warnings python_coverage] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/635 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #1847 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1847
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<GitHub146> [artiq] gkasprow commented on issue #854: OK, I got 2 clocks running and some packets while DV line is high... https://github.com/m-labs/artiq/issues/854#issuecomment-353407812
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<GitHub102> [artiq] whitequark commented on issue #879: I believe the purpose of this is setting the path to proxy bitstreams. Since we now build packages exclusively on the buildbot it is no longer necessary. https://github.com/m-labs/artiq/issues/879#issuecomment-353417306
<GitHub125> [artiq] whitequark commented on issue #879: I believe the purpose of this is setting the environment variable containing the path to proxy bitstreams. Since we now build packages exclusively on the buildbot it is no longer necessary. https://github.com/m-labs/artiq/issues/879#issuecomment-353417306
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<GitHub195> [artiq] jordens commented on issue #879: Don't know where that came from. Fwiw can be removed. https://github.com/m-labs/artiq/issues/879#issuecomment-353439906
<GitHub89> [artiq] enjoy-digital commented on issue #856: I'm looking at that. https://github.com/m-labs/artiq/issues/856#issuecomment-353449733
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<GitHub154> [artiq] enjoy-digital pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/86825a852c8a8577ec3b37b79a171576d758e69a
<GitHub154> artiq/master 86825a8 Florent Kermarrec: gateware/targets/sayma_rtm: add false path between cd_sys and cd_clk200
<bb-m-labs> build #967 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/967
<bb-m-labs> build #636 of artiq-win64-test is complete: Warnings [warnings python_coverage] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/636 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
<bb-m-labs> build #1848 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1848
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<GitHub53> [artiq] enjoy-digital commented on issue #856: @sbourdeauducq: i should have fix timing on RTM design (a false path was missing). It seems I'm not able to reproduce easily the issue.... https://github.com/m-labs/artiq/issues/856#issuecomment-353484600
<GitHub150> [artiq] enjoy-digital commented on issue #856: @sbourdeauducq: i should have fixed timing on RTM design (a false path was missing). It seems I'm not able to reproduce easily the issue.... https://github.com/m-labs/artiq/issues/856#issuecomment-353484600
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