sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> cr1901_modern, thanks
<sb0> rjo, ping re. 9910 vs. 9912
<GitHub184> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/migen/commit/cfd6fcdd4763ad16a570b2694eb51d946f1b0924
<GitHub184> migen/master cfd6fcd William D. Jones: fhdl/tracer: Support Python 3.5 `CALL_FUNCTION_KW` and `CALL_FUNCTION_VAR_KW`...
<bb-m-labs> build #217 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/217
<GitHub162> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/migen/commit/e7ed194d476541fbe2027b975856be8f6d379cd8
<GitHub162> migen/master e7ed194 Sebastien Bourdeauducq: sayma_amc: do not constrain Ethernet clocks
<GitHub147> [misoc] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/misoc/commit/e7f3197179a644d77f2191f3aebedf9303c86c41
<GitHub147> misoc/master e7f3197 Sebastien Bourdeauducq: sayma_amc: fix MII clock constraints
<bb-m-labs> build #218 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/218
<bb-m-labs> build #308 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/308
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<rjo> sb0: afaict both chips are of similar maturity.
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<cr1901_modern> felix_: https://github.com/m-labs/migen/pull/98 Please test this
<GitHub12> [artiq] jonaskeller opened issue #877: FPGA stops responding to ethernet after a few hours https://github.com/m-labs/artiq/issues/877
<cr1901_modern> On second thought, nevermind... it's still broken in the edge cases
<cr1901_modern> Okay, muuuuch better. felix_: If you want to test Python 3.6, I just force-pushed the _actual_ fix :)
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<felix_> i'll try to test that maybe tomorrow
<GitHub50> [artiq] gkasprow commented on issue #854: @sbourdeauducq The PHY supports RX CLK TX CLK clock inputs only in 100mbit DTE mode.... https://github.com/m-labs/artiq/issues/854#issuecomment-353180200
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<dlrobertson> whitequark: 1) sorry for the delay on #35, going to start now
<dlrobertson> 2) what was the motivation for the change in the neighbor cache to force the use of BTreeMap instead of the trait?
<dlrobertson> just curious
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<GitHub186> [artiq] sbourdeauducq commented on issue #854: Regular MII. https://github.com/m-labs/artiq/issues/854#issuecomment-353203141
<GitHub169> [artiq] sbourdeauducq commented on issue #854: Regular MII + DTE MII. https://github.com/m-labs/artiq/issues/854#issuecomment-353203141
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