sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub8> [artiq] sbourdeauducq commented on issue #875: Does the isMinimized test do anything? (other than hint what this code is for) https://github.com/m-labs/artiq/pull/875#issuecomment-352145503
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<GitHub190> [artiq] klickverbot commented on issue #875: > Does the isMinimized test do anything? (other than hint what this code is for)... https://github.com/m-labs/artiq/pull/875#issuecomment-352146106
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<sb0> from the data corruption I'm getting, it seems that the IO timing of RGMII is fucked and Greg's design just works by chance
<sb0> whitequark, can I get a good phase shift resolution out of the si5324 too?
<sb0> range 4ns, maximum phase shift resolution
<sb0> er, 8ns of range
<sb0> oh there was a 125MHz setting in the test repo...
<sb0> bios netboot won't work though, unless the bios also does the si5324 hack...
<sb0> alternatively MII has 10x the timing margin, but that requires touching the MMC
<sb0> and 100Mbps only
<GitHub163> [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/migen/commit/775572ea79d9c181caa2af9f1f3fd7f7cd578249
<GitHub163> migen/master 775572e Sebastien Bourdeauducq: sayma_amc: add si5324_clkout_fabric
<bb-m-labs> build #215 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/215
<whitequark> sb0: I would like to vote in favor of keeping bios netboot potentially working
<GitHub88> [misoc] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/misoc/commit/15ddb69f9f42f12b69d7a2d9e443217db1b8abc2
<GitHub88> misoc/master 15ddb69 Sebastien Bourdeauducq: sayma_amc: send RGMII RX clock through Si5324
<bb-m-labs> build #302 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/302
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<GitHub81> [misoc] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/misoc/commit/e26813cd5f51bbd10e18091615b8dd40c8b2cd46
<GitHub81> misoc/master e26813c Sebastien Bourdeauducq: sayma_amc: fix platform.request calls
<GitHub144> [misoc] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/misoc/commit/2fcb2f51b30424d7c751a8b5bebad85644c92e7a
<GitHub144> misoc/master 2fcb2f5 Sebastien Bourdeauducq: sayma_amc: add missing import
<bb-m-labs> build #303 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/303
<bb-m-labs> build #304 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/304
<GitHub117> [misoc] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/misoc/commit/f509de0cbd63947535741573881f40a2b23d4ab7
<GitHub117> misoc/master f509de0 Sebastien Bourdeauducq: sayma_amc: remove RGMII CLOCK_DEDICATED_ROUTE when rerouting
<bb-m-labs> build #305 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/305
<sb0> so, the sayma si5324 works (I think that's something that hadn't been tested...)
<GitHub27> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/2b01aa22b63dee6902cb5d4075d5ccde5800cb66
<GitHub27> artiq/master 2b01aa2 Sebastien Bourdeauducq: sayma: set up Si5324 for RGMII clock rerouting
<rjo> i seem to remember that greg tested that.
<whitequark> sb0: how does clocking work on sayma now?
<sb0> whitequark, what part?
<whitequark> I don't quite get what are you doing with Si5324 and Ethernet
<sb0> greg connected the ethernet phy clock to a non-clock-capable fpga pin
<sb0> this causes xilinx stuff to misbehave even more than usual
<sb0> e.g. probably causes a lot of non-determinism in I/O timing between vivado runs. and with data rate of 250Mbps, we really don't need that
<sb0> so the workaround I'm trying right now is to send the clock to the si5324, which then drives it back into the FPGA using a clock-capable pin
<bb-m-labs> build #957 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/957
<sb0> oh
<sb0> For system-level deb
<sb0> ugging, a bypass mode is
<sb0> available which drives the out
<sb0> put clock directly from the
<sb0> input clock, bypassing the internal DSPLL.
<bb-m-labs> build #629 of artiq-win64-test is complete: Warnings [warnings python_coverage] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/629 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #1841 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1841
<sb0> sigh, now I can no longer lock the si5324 to the rx clock, even with the original code that worked
<sb0> what is going on...
<whitequark> sb0: why did greg do that?
<sb0> mistake
<GitHub45> [artiq] sbourdeauducq commented on issue #854: > Why did you clock all the IDDRE1 with the inverted clock gmii_rx_clk_b?... https://github.com/m-labs/artiq/issues/854#issuecomment-352196290
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<GitHub118> [artiq] gkasprow commented on issue #854: I wanted to swap nibbles. I didn't try that since existing solution works. If it really helps I can check it but I'd have to assemble the setup. https://github.com/m-labs/artiq/issues/854#issuecomment-352199298
<GitHub20> [smoltcp] dlrobertson commented on pull request #75 83a42eb: Most the other `Packet` types document the methods. The `Repr` is documented well, but it would be nice if this was as well. https://github.com/m-labs/smoltcp/pull/75#discussion_r157347911
<GitHub152> [smoltcp] dlrobertson commented on pull request #75 83a42eb: The other `Repr` and `Packet` types in `wire` have tests. It might be good to add some basic unit tests. https://github.com/m-labs/smoltcp/pull/75#discussion_r157347736
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<dlrobertson> Hi!
<dlrobertson> just noticed you guys had an IRC channel
<dlrobertson> is this a good place to discuss things smoltcp related that do not warrant a GitHub issue?
<whitequark> sure
<dlrobertson> cool, we were discussing that on the redox-os #networking channel
<dlrobertson> btw if you have anything you need help with smoltcp related, feel free to ping me... i have some extra cycles
<whitequark> alright, let me push some work in progress and I have a few things for you
<dlrobertson> +1
<GitHub168> [smoltcp] whitequark pushed 3 new commits to master: https://github.com/m-labs/smoltcp/compare/8d0913652a7f...97d262ed54eb
<GitHub168> smoltcp/master fe94691 whitequark: Fix clocking code in the loopback example.
<GitHub168> smoltcp/master b168036 whitequark: Rework the pretty printer to avoid superfluous trailing newlines.
<GitHub168> smoltcp/master 97d262e whitequark: Style. NFC.
<travis-ci> m-labs/smoltcp#477 (master - 97d262e : whitequark): The build passed.
<GitHub128> [artiq] whitequark pushed 3 new commits to master: https://github.com/m-labs/artiq/compare/2b01aa22b63d...aaba36be7a55
<GitHub128> artiq/master 4a9d8c9 whitequark: runtime: fix a warning.
<GitHub128> artiq/master 8cece4f whitequark: runtime: hotswap slightly more carefully....
<GitHub128> artiq/master aaba36b whitequark: runtime: log moninj messages at TRACE level, like all others.
<GitHub155> [smoltcp] whitequark commented on pull request #89 0a5d2a1: describing https://github.com/m-labs/smoltcp/pull/89#discussion_r157353011
<GitHub36> [smoltcp] whitequark commented on pull request #89 0a5d2a1: Maybe `pretty_print_ip_payload`? https://github.com/m-labs/smoltcp/pull/89#discussion_r157353077
<GitHub69> [smoltcp] whitequark commented on pull request #89 0a5d2a1: `as` binds very tight so the parens are not necessary. https://github.com/m-labs/smoltcp/pull/89#discussion_r157353028
<GitHub171> [smoltcp] whitequark commented on pull request #89 0a5d2a1: In general I'm not too worried about copy/paste in `smoltcp::wire`, various magic to reduce amount of code is an explicit non-goal if you take a look at README. https://github.com/m-labs/smoltcp/pull/89#discussion_r157353219
<GitHub27> [smoltcp] whitequark commented on pull request #89 0a5d2a1: Note that this `\n` is not necessary now. https://github.com/m-labs/smoltcp/pull/89#discussion_r157353076
<GitHub87> [smoltcp] whitequark commented on pull request #89 0a5d2a1: I don't think this branch is necessary, the upper layer will display the packet type. E.g. it's in the ethertype field for Ethernet. https://github.com/m-labs/smoltcp/pull/89#discussion_r157353051
<bb-m-labs> build #958 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/958
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