<GitHub99>
[artiq] jonaskeller commented on issue #877: Just an update: I've been monitoring an idle FPGA every night this week and haven't seen it crash yet (using 3.2 py_1+gita4337944). Given that it used to happen multiple times a day when I opened this issue, it seems likely that the problem is fixed. https://github.com/m-labs/artiq/issues/877#issuecomment-357397429
<GitHub126>
[smoltcp] dlrobertson commented on issue #118: > The very first PR should probably just handle IPv6 packets and forward them to the socket. The second should probably handle sending packets via RawSocket.... https://github.com/m-labs/smoltcp/pull/118#issuecomment-357400490
<ohsix>
the post-2008 delphi is wild, string conversion every other line
<GitHub77>
[smoltcp] dlrobertson commented on pull request #118 20c1021: I use an ipv6 specific variable below and this block is run if `proto-ipv4` is enabled, so if `proto-ipv4` is enabled but `proto-ipv6` is not you'll get a compile failure. https://github.com/m-labs/smoltcp/pull/118#discussion_r161361599
<loozol>
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<loozol>
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<loozol>
â–„â–„â–„â–„â–„â–„â–„â–„â–„â–„â–„â–„â–„â–„â–„ PLEASE JOIN #RIPASSHURT FOR A MEMORIAL CONCERNING ASSHURT (DUE TO THE SENSITIVE NATURE OF THIS POST EL HAS APPROVED THIS MESSAGE. EL CAN BE FOUND IN #FREENODE) jyhzhj: adamgreig kyak key2 â–„â–„â–„â–„â–„â–„â–„â–„â–„â–„â–„â
<sb0>
hartytp, so serwb works well for you?
<sb0>
and still no 1.8v failures?
<sb0>
hartytp, by the way, this is why i like the si5324: you merely give it the divider and loop bandwidth settings and then it does its thing.
<sb0>
and I haven't found a single bug or lock-up with it