sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<cjbe__> sb0: FYI on Kasli the Si5324 communication fails ("failed to ack value") - I am using a current build
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<sb0> cjbe__, could be the 5324 not acking the reset write
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<sb0> rjo, smaller tag width as explained (or just luck)
<sb0> cjbe__, yes, that's exactly what it is
<sb0> Si5324 works fine and locks when you work around that
<sb0> turns out, Si also does typical silicon vendor bullshit, sometimes
<GitHub29> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/0d2f89db5366ff52f618d9fe1789a6242359a99c
<GitHub29> artiq/master 0d2f89d Sebastien Bourdeauducq: si5324: chip does not ack RST_REG write
<GitHub199> [sinara] marmeladapk pushed 1 new commit to master: https://git.io/vN66s
<GitHub199> sinara/master 155938a Paweł: Kasli v1.1rc1...
<bb-m-labs> build #1141 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1141
<bb-m-labs> build #709 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/709
<bb-m-labs> build #1997 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1997
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<sb0> cjbe__, there are no SFP ports on the switch you sent to Hong Kong
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<GitHub40> [artiq] sbourdeauducq commented on issue #854: Are you sure your ``I`` command works? Does this sequence of events result in a working PHY:... https://github.com/m-labs/artiq/issues/854#issuecomment-360375637
<GitHub188> [artiq] sbourdeauducq commented on issue #854: How are you generating the clock in your test bitstream? Have you installed ARTIQ now? https://github.com/m-labs/artiq/issues/854#issuecomment-360376360
<GitHub4> [artiq] sbourdeauducq commented on issue #854: Are you sure your ``I`` command works? Does this sequence of events result in a working PHY:... https://github.com/m-labs/artiq/issues/854#issuecomment-360375637
<GitHub73> [artiq] sbourdeauducq commented on issue #854: How are you generating the clock in your test bitstream? How are you loading that bitstream? Have you installed ARTIQ now? https://github.com/m-labs/artiq/issues/854#issuecomment-360376360
<GitHub174> [artiq] sbourdeauducq commented on issue #854: Are you sure your ``I`` command works? Does this sequence of events result in a working PHY:... https://github.com/m-labs/artiq/issues/854#issuecomment-360375637
<GitHub178> [artiq] sbourdeauducq commented on issue #854: The following FPGA design does not result in a link being established.... https://github.com/m-labs/artiq/issues/854#issuecomment-360380884
<GitHub65> [artiq] sbourdeauducq commented on issue #854: Are you sure your ``I`` command works? Does this sequence of events result in a working PHY:... https://github.com/m-labs/artiq/issues/854#issuecomment-360375637
<GitHub184> [artiq] sbourdeauducq commented on issue #854: The following FPGA design does not result in a link being established.... https://github.com/m-labs/artiq/issues/854#issuecomment-360380884
<GitHub190> [artiq] sbourdeauducq commented on issue #854: The following FPGA design does not result in a link being established.... https://github.com/m-labs/artiq/issues/854#issuecomment-360380884
<sb0> well, uh, somehow I received two kaslis
<cjbe__> sb0: I am using a 1000BASE-T SFP to connect the 1000BASE-T switch (https://www.fs.com/products/11773.html)
<GitHub179> [artiq] gkasprow commented on issue #854: @sbourdeauducq I also generate 125MHz from 50MHz clock.... https://github.com/m-labs/artiq/issues/854#issuecomment-360421242
<GitHub177> [artiq] gkasprow commented on issue #854: do you get response: ... https://github.com/m-labs/artiq/issues/854#issuecomment-360421841
<GitHub42> [artiq] gkasprow commented on issue #854: do you get response: ... https://github.com/m-labs/artiq/issues/854#issuecomment-360421841
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<GitHub142> [artiq] sbourdeauducq commented on issue #854: Yes, and the firmware responds to ``I``, but no link.... https://github.com/m-labs/artiq/issues/854#issuecomment-360423277
<sb0> cjbe__, is it a problem with the SFP or the switch?
<cjbe__> sb0: not sure - I suspect the switch is at an edge case in the specification, as this is the one with the odd preamble. The 1000BASE-T SFP works with a different switch. Any suggestions for isolating the problem on my end?
<sb0> cjbe__, with the same SFP and a different switch, does it work?
<cjbe__> sb0: yes - the same SFP works with another switch
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<sb0> hm, strange
<sb0> and the problem you're seeing is no link LED anywhere?
<cjbe__> correct
<GitHub137> [artiq] gkasprow commented on issue #854: I'm just castrating my design and once it compiles I will test it and send it to you. https://github.com/m-labs/artiq/issues/854#issuecomment-360430587
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<GitHub56> [artiq] gkasprow commented on issue #854: I hate xilinx. Compilation of almost empty project takes 30 mins! https://github.com/m-labs/artiq/issues/854#issuecomment-360446465
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<GitHub183> [artiq] gkasprow commented on issue #854: [here](https://www.dropbox.com/sh/mkr0qxkwhp8crsh/AAD9QnIeOJNIe8zLGAZL66d1a?dl=0) is the design. There is just MMCM generating 125MHz and FORTH processor, but it is not connected to Ethernet.... https://github.com/m-labs/artiq/issues/854#issuecomment-360451624
<GitHub161> [artiq] gkasprow commented on issue #854: And the LINK is on. https://github.com/m-labs/artiq/issues/854#issuecomment-360451886
<sb0> rjo, can you locate greg's ethernet test here? https://www.dropbox.com/sh/mkr0qxkwhp8crsh/AAD9QnIeOJNIe8zLGAZL66d1a?dl=0
<sb0> geez...
<sb0> I asked for a minimal design, again this is a huge mess with hundreds of files
<sb0> there's even a ddr controller in there
<GitHub2> [artiq] sbourdeauducq commented on issue #854: Where? There are hundreds of files in that dropbox. https://github.com/m-labs/artiq/issues/854#issuecomment-360454087
<GitHub169> [artiq] sbourdeauducq commented on issue #854: This is a terrible mess. Can you send me the bitfile or something? Can you boil it down to a few files (.v/.xdc/.tcl)? Or even better: can you try MiSoC/ARTIQ on your board? https://github.com/m-labs/artiq/issues/854#issuecomment-360454622
<GitHub20> [artiq] gkasprow commented on issue #854: source is in ... https://github.com/m-labs/artiq/issues/854#issuecomment-360454999
<GitHub48> [artiq] gkasprow commented on issue #854: it's vivado who does such mess. Dropbox does mirror of my entire 1TB hard disk https://github.com/m-labs/artiq/issues/854#issuecomment-360455167
<GitHub87> [artiq] sbourdeauducq commented on issue #854: > bit is here:... https://github.com/m-labs/artiq/issues/854#issuecomment-360456520
<GitHub57> [artiq] gkasprow commented on issue #854: At the moment I'm debugging HMC830 issue, will try it later. https://github.com/m-labs/artiq/issues/854#issuecomment-360456920
<GitHub41> [artiq] sbourdeauducq commented on issue #854: > bit is here:... https://github.com/m-labs/artiq/issues/854#issuecomment-360456520
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<GitHub189> [artiq] gkasprow commented on issue #860: I delivered 100MHz to HMC, loaded 👍 0 $0 $20 spi_hmc830 .... https://github.com/m-labs/artiq/issues/860#issuecomment-360469058
<GitHub199> [artiq] gkasprow commented on issue #860: I delivered 100MHz to HMC, loaded 0 $0 $20 spi_hmc830 .... https://github.com/m-labs/artiq/issues/860#issuecomment-360469058
<GitHub108> [artiq] gkasprow commented on issue #860: when I read 0x12H I get ... https://github.com/m-labs/artiq/issues/860#issuecomment-360469961
<GitHub55> [artiq] gkasprow commented on issue #860: I delivered 100MHz to HMC, loaded ... https://github.com/m-labs/artiq/issues/860#issuecomment-360469058
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<GitHub90> [artiq] sbourdeauducq commented on issue #860: Yes, sometimes it works here, too. Have you tried with artiq? https://github.com/m-labs/artiq/issues/860#issuecomment-360476074
<GitHub36> [artiq] gkasprow commented on issue #860: not yet https://github.com/m-labs/artiq/issues/860#issuecomment-360478499
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<GitHub126> [artiq] hartytp commented on issue #854: > At the moment I'm debugging HMC830 issue, will try it later.... https://github.com/m-labs/artiq/issues/854#issuecomment-360489780
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<GitHub171> [artiq] hartytp commented on issue #860: @gkasprow how many bits are you transferring for each of those writes? https://github.com/m-labs/artiq/issues/860#issuecomment-360490776
<GitHub70> [artiq] gkasprow commented on issue #860: I use 32 bits - this is bit-bang SPI but the code is executed really fast. I get a few MHz SPI clock... https://github.com/m-labs/artiq/issues/860#issuecomment-360494337
<GitHub20> [artiq] gkasprow commented on issue #854: I'm trying to make ARTIQ running right now
<GitHub141> [artiq] sbourdeauducq commented on issue #854: To generate bitstreams with different TX clock phases relatively quickly, you can use this script:... https://github.com/m-labs/artiq/issues/854#issuecomment-360497764
<GitHub156> [artiq] gkasprow commented on issue #854: I managed to load the artiq bits to both FPGAs
<GitHub67> [artiq] sbourdeauducq commented on issue #854: Do you see the TX clock with the scope?... https://github.com/m-labs/artiq/issues/854#issuecomment-360503055
<GitHub42> [artiq] gkasprow commented on issue #854: OK, I got the LINK LED on. Used wrong SATA socket:)
<GitHub144> [artiq] sbourdeauducq commented on issue #854: OK. Interesting that it doesn't work at all here (no link). If you play with the TX phase using the script above, you should in theory be able to ping the board with no packet loss. https://github.com/m-labs/artiq/issues/854#issuecomment-360503621
<GitHub175> [artiq] sbourdeauducq commented on issue #854: OK. Interesting that it doesn't work at all here (no link). If you play with the TX phase using the script above, you should in theory be able to ping the board with no packet loss.... https://github.com/m-labs/artiq/issues/854#issuecomment-360503621
<GitHub4> [artiq] sbourdeauducq commented on issue #854: OK. Interesting that it doesn't work at all here (no link). If you play with the TX phase using the script above, you should in theory be able to ping the board with no packet loss. I assume you have connected the RX clock to GPIO0.... https://github.com/m-labs/artiq/issues/854#issuecomment-360503621
<GitHub145> [artiq] gkasprow commented on issue #854: Funny thing, there is Rx clock but no Tx clock, but the LINK is on.
<GitHub101> [artiq] gkasprow commented on issue #854: DONE LED is also on, so the bit was loaded.
<GitHub45> [artiq] sbourdeauducq commented on issue #854: Are you sure you flashed your latest MMC firmware?... https://github.com/m-labs/artiq/issues/854#issuecomment-360505807
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<GitHub82> [artiq] gkasprow commented on issue #854: I have only one board here ::)
<GitHub142> [artiq] gkasprow commented on issue #854: It's one week old
<GitHub41> [artiq] sbourdeauducq commented on issue #854: > It's one week old... https://github.com/m-labs/artiq/issues/854#issuecomment-360512344
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<GitHub17> [sinara] jordens tagged Kasli/v1.1rc1 at 967c93d: https://git.io/vNiDg
<GitHub190> [artiq] gkasprow commented on issue #854: Pawel is helping me with this... https://github.com/m-labs/artiq/issues/854#issuecomment-360515979
<GitHub142> [artiq] marmeladapk commented on issue #854: I pulled latest version 10 minutes ago and I'm building sayma_rtm and sayma_amc targets right now. https://github.com/m-labs/artiq/issues/854#issuecomment-360516423
<GitHub123> [artiq] marmeladapk commented on issue #854: >git rev-parse --short @ ... https://github.com/m-labs/artiq/issues/854#issuecomment-360518263
<GitHub113> [artiq] marmeladapk commented on issue #854: @sbourdeauducq ... https://github.com/m-labs/artiq/issues/854#issuecomment-360518263
<GitHub111> [artiq] sbourdeauducq commented on issue #854: Get the JESD core from git (https://github.com/m-labs/jesd204b), not the conda package. Considering how many people run into this issue, I should probably update the conda package...... https://github.com/m-labs/artiq/issues/854#issuecomment-360518701
<GitHub69> [artiq] marmeladapk commented on issue #854: @sbourdeauducq Please, could you update conda package? I'm busy with Kasli and I don't want to figure out new configuration. https://github.com/m-labs/artiq/issues/854#issuecomment-360519557
<GitHub15> [artiq] marmeladapk commented on issue #854: @sbourdeauducq Please, could you update conda package? I'm busy with Kasli and I don't want to figure out new configuration. I'd be grateful. https://github.com/m-labs/artiq/issues/854#issuecomment-360519557
<GitHub6> [artiq] sbourdeauducq commented on issue #854: It's just 3 commands:... https://github.com/m-labs/artiq/issues/854#issuecomment-360520166
<GitHub106> [artiq] jbqubit opened issue #906: JESD core conda update https://github.com/m-labs/artiq/issues/906
<GitHub12> [artiq] jbqubit commented on issue #898: > Accessing AMC hardware without the RTM connected is not supported.... https://github.com/m-labs/artiq/issues/898#issuecomment-360531197
<GitHub28> [artiq] whitequark commented on issue #898: There will be one option after my last round of `artiq_flash` changes. https://github.com/m-labs/artiq/issues/898#issuecomment-360531504
<GitHub30> [artiq] jbqubit commented on issue #898: @whitequark Did you try building .bit from scratch and then using ```artiq_flash```? From status 3 days ago things were far from seamless. https://github.com/m-labs/artiq/issues/898#issuecomment-360531526
<GitHub103> [artiq] jbqubit commented on issue #856: @enjoy-digital IT's indeed odd that 1.25 Gbps worked [some time ago](https://github.com/enjoy-digital/sayma_test) but now doesn't. Is serwb now working reliably at 635 Mbps? https://github.com/m-labs/artiq/issues/856#issuecomment-360532747
<GitHub160> [artiq] whitequark commented on issue #898: No. It doesn't really matter because of the rewrite I mentioned. https://github.com/m-labs/artiq/issues/898#issuecomment-360533364
<GitHub162> [artiq] sbourdeauducq closed issue #906: JESD core conda update https://github.com/m-labs/artiq/issues/906
<GitHub64> [misoc] jordens pushed 1 new commit to master: https://github.com/m-labs/misoc/commit/cb8e314c7515eade46f5bcde4e48903d7ec92490
<GitHub64> misoc/master cb8e314 Robert Jordens: spi: fix clock divider selection...
<bb-m-labs> build #377 of misoc is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/377
<GitHub170> [artiq] jordens pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/c9b36e355997fe3b0ce294e6c4d77f14a00a9394
<GitHub170> artiq/master c9b36e3 Robert Jordens: conda: bump misoc, close #905
<GitHub55> [artiq] jordens closed issue #905: spi clock divider (chained read) https://github.com/m-labs/artiq/issues/905
<GitHub161> [artiq] jordens pushed 1 new commit to release-3: https://github.com/m-labs/artiq/commit/a85fd13c21b3f635e58a7ce60303b970f23dd5ae
<GitHub161> artiq/release-3 a85fd13 Robert Jordens: conda: bump misoc, close #905...
<bb-m-labs> build #1142 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1142
<bb-m-labs> build #1998 of artiq is complete: Failure [failed python_coverage_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1998 blamelist: Robert Jordens <rj@m-labs.hk>
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<bb-m-labs> build #1999 of artiq is complete: Failure [failed python_coverage] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1999 blamelist: Robert Jordens <rj@m-labs.hk>
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<bb-m-labs> build #2000 of artiq is complete: Failure [failed python_coverage] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2000 blamelist: Robert Jordens <rj@m-labs.hk>
<bb-m-labs> build #1143 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/1143
<bb-m-labs> build #710 of artiq-win64-test is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-win64-test/builds/710
<bb-m-labs> build #2001 of artiq is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2001
<GitHub64> [artiq] enjoy-digital commented on issue #856: @jbqubit: i don't think serwb 1.25Gbps has a different behaviour than before. Just that it seems not reliable with some of the boards at 1.25Gbps and seems to be reliable with all boards we tested at 625Mbps. ... https://github.com/m-labs/artiq/issues/856#issuecomment-360623281
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