sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> _florent_, in the wishbone cache, you say: "Cachesize (in 32-bit words)"
<sb0> why did you choose 32-bit words and not bytes?
<sb0> is that even 32-bit words...? reading the code I'm not sure...
<sb0> it seems to be dependent on the data widths of the wishbone buses you connect
<GitHub177> [artiq] whitequark pushed 2 new commits to master: http://git.io/v06ts
<GitHub177> artiq/master 8751d2e whitequark: Delay.{expr→interval}.
<GitHub177> artiq/master 35acc33 whitequark: validators.escape: don't fail on quoted values in lhs.
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<GitHub15> [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/v06cR
<GitHub15> misoc/master fddf0f2 Sebastien Bourdeauducq: Refactor SDRAM integration...
<GitHub162> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/v06cg
<GitHub162> artiq/master 3386082 Sebastien Bourdeauducq: gateware/soc: use new SDRAM API call
<GitHub189> [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/v06lQ
<GitHub189> misoc/master 17cfcbe Sebastien Bourdeauducq: README: update
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<cr1901_modern> sb0: Yes, I did copy signals from pyqtgraph. And you're right that it was a bad idea. If I move my "import scanwidget" to above "from quamash..." imports in main.py, it breaks.
<cr1901_modern> QtCore.Signal appears to be a PySide thing that quamash seems to accept as an alias
<sb0> _florent_, ysionnea1, others: if you are willing to maintain misoc targets (test them regularly and fix any problems), can you add yourself to this page: https://github.com/m-labs/misoc/wiki
<sb0> ideally, those boards would receive at least bi-yearly testing...
<GitHub189> [artiq] whitequark pushed 1 new commit to master: http://git.io/v06RI
<GitHub189> artiq/master f8eaeaa whitequark: compiler: explicitly represent loops in IR.
<cr1901_modern> sb0: Fortunately, PyQt's new syntax for signals supports both Qt4 and 5, so I'll just use that from now on. My fault :P.
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<GitHub188> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/v06KN
<GitHub188> migen/master 7591c09 Sebastien Bourdeauducq: Revert "README.md->rst"...
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<mithro> cr1901_modern: ping? shenki has some minispartan6 questions in #timvideos
<cr1901_modern> mithro: Ack. As soon as IRC client starts behaving
<_florent_> sb0: for Cachesize, i think i didn't wanted to touch what was done done in wishbone2lasmi
<_florent_> sb0: but we added genericity on width after that an comment is not up to date
<_florent_> sb0: we should probably define cachesize in bytes
<GitHub145> [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/v0ivX
<GitHub145> misoc/master 2aa4fb7 Sebastien Bourdeauducq: pack memory maps
<_florent_> sb0: about the target, I can take care of the de0nano and minispartan6
<GitHub13> [artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/v0iJv
<GitHub13> artiq/master afaad27 Sebastien Bourdeauducq: rtio/analyzer: fix superficial mistakes
<GitHub13> artiq/master 4def561 Sebastien Bourdeauducq: targets: integrate RTIO analyzer
<bb-m-labs_> build #24 of misoc is complete: Failure [failed] Build details are at http://m-labs-buildserver.lan/buildbot/builders/misoc/builds/24
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<bb-m-labs_> build #25 of misoc is complete: Failure [failed] Build details are at http://m-labs-buildserver.lan/buildbot/builders/misoc/builds/25
<bb-m-labs_> build #14 of artiq-kc705-nist_qc1 is complete: Failure [failed conda_build] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq-kc705-nist_qc1/builds/14
<bb-m-labs_> build #10 of artiq-pipistrello-nist_qc1 is complete: Failure [failed conda_build] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq-pipistrello-nist_qc1/builds/10
<bb-m-labs_> build #14 of artiq-kc705-nist_qc2 is complete: Failure [failed conda_build] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq-kc705-nist_qc2/builds/14
<bb-m-labs_> build #26 of misoc is complete: Failure [failed] Build details are at http://m-labs-buildserver.lan/buildbot/builders/misoc/builds/26
<GitHub50> [misoc] whitequark pushed 1 new commit to master: http://git.io/v0iqA
<GitHub50> misoc/master 4c73a2a whitequark: Fix software/unwinder submodule.
<bb-m-labs_> build #27 of misoc is complete: Success [build successful] Build details are at http://m-labs-buildserver.lan/buildbot/builders/misoc/builds/27
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<bb-m-labs_> build #15 of artiq-kc705-nist_qc2 is complete: Success [build successful] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq-kc705-nist_qc2/builds/15
<bb-m-labs_> build #15 of artiq-kc705-nist_qc1 is complete: Success [build successful] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq-kc705-nist_qc1/builds/15
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<GitHub92> [artiq] whitequark pushed 2 new commits to master: http://git.io/v0iPf
<GitHub92> artiq/master 69cdeaf whitequark: transforms.interleaver: don't fail on degenerate parallel blocks.
<GitHub92> artiq/master 2570932 whitequark: transforms.interleaver: don't fail on delay-free loops/conditionals.
<GitHub110> [artiq] whitequark pushed 1 new commit to master: http://git.io/v0iPo
<GitHub110> artiq/master 142b9b0 whitequark: lit-test: add tests for control flow in parallel blocks.
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<GitHub4> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/v0iMW
<GitHub4> artiq/master 5e38cad Sebastien Bourdeauducq: test/coredevice: partial update to new APIs
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<sb0> so the Oxford artiq is there: https://github.com/cjbe/artiq
<GitHub43> [artiq] whitequark pushed 2 new commits to master: http://git.io/v013K
<GitHub43> artiq/master 8cb7844 whitequark: transforms.interleaver: unroll loops.
<GitHub43> artiq/master 5dd1fc9 whitequark: transforms.dead_code_eliminator: also remove dead instructions.
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<rjo> did anybody other than _florent_ in litesata play with the xilinx transcievers in migen?
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<rjo> anybody else see massive timing problems on artiq/kc705 or is working on them?