04:41 <GitHub173> [artiq] whitequark pushed 1 new commit to master: http://git.io/vEgE1

04:41 <GitHub173> artiq/master 690b2fd whitequark: transforms.artiq_ir_generator: fix optarg codegen (closes #205).

07:03 <GitHub40> [artiq] whitequark pushed 2 new commits to master: http://git.io/vEgMC

07:03 <GitHub40> artiq/master 33c3b33 whitequark: ir: keep loc when copying.

07:03 <GitHub40> artiq/master 082e9e2 whitequark: compiler: do not associate SSA values with iodelay even when inlining....

07:26 <mithro> Merry Xmas!

07:27 <mithro> sb0: I've been playing with the FSM stuff a bit more and was wondering, is there a way to "reset" the FSM back into the initial state (from any state) without putting a 'If(rst = 1, NextState("INITIAL"))' in every stage?

07:33 <mithro> Looks like there is a "reset_state" in the module but wasn't sure if that was its purpose

07:35 <mithro> It also looks like you can have multiple fsm.act( statements per state...

09:13 <_florent_> Merry Christmas

09:13 <_florent_> mithro: you can use something like this: https://github.com/m-labs/misoc/blob/master/misoc/cores/dvi_sampler/edid.py#L194

09:24 <mithro> _florent_: feels like something which might benefit being part of the FSM module

09:27 <_florent_> You can also use InsertReset:

09:27 <_florent_> fsm = InsertReset(FSM(reset_state="IDLE"))

09:27 <_florent_> then you have a fsm.reset signal that you can use

09:59 <whitequark> EvilSpirit: hi

10:28 <cr1901_modern> Large trout. That's certainly not a welcome I would expect in such a refined and professional setting as #m-labs

19:17 <GitHub187> [artiq] whitequark pushed 2 new commits to master: http://git.io/vEaHJ

19:17 <GitHub187> artiq/master 8051fe9 whitequark: Commit missing parts of 082e9e20dd.

19:17 <GitHub187> artiq/master 502e570 whitequark: compiler: embed host exception constructors as such (fixes #204).