03:53 <mithro> Human psychology is funny, x3csprog is objectively slower at flashing the pipistrello device but it feels faster because it outputs progress as it does so

04:18 <sb0> whitequark,

04:18 <sb0> <artiq>/test/coredevice/portability.py:103:17: fatal: unexpected indent: expected (, *, +, -, ..., @, False, None, True, [, assert, break, class, complex, continue, def, del, exec, float, for, from, global, ident, if, import, int, lambda, nonlocal, not, pass, print, raise, return, strbegin, try, while, with, yield, { or ~

04:18 <sb0> # with sequential:

04:18 <sb0> ^

04:19 <sb0> so many compiler problems ...

04:40 <sb0> whitequark, test_pulses mostly doesn't fail on the host, what is essentially happening is that your compiler incorrectly maps the different instances of _PulseLogger to a single one on the device

04:40 <sb0> all pulses go to channel A

04:40 <sb0> instead of A, B, C and D

04:44 <GitHub17> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vE9P8

04:44 <GitHub17> artiq/master aa29def Sebastien Bourdeauducq: test/coredevice/test_pulses: fix first_timestamp

04:47 <sb0> whitequark, https://github.com/m-labs/artiq/issues/211

07:40 <sb0> of course, the xst placer craps out when you connect both inputs of a PLL to another PLL and a BUFR

07:45 <sb0> seriously, i've never seen that thing work correctly when compiling anything else than a xilinx reference design

08:11 <sb0> and now this

08:11 <sb0> WARNING:PhysDesignRules:2260 - Unsupported PLLE2_ADV configuration. The driver

08:11 <sb0> of the CLKIN2 pin (BUFR) of PLLE2_ADV comp PLLE2_ADV with COMPENSATION mode

08:11 <sb0> BUF_IN, must be the same type of driver as the CLKIN1 pin (BUFG).

08:22 <GitHub136> [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/vEHOw

08:22 <GitHub136> misoc/master 1887942 Sebastien Bourdeauducq: targets/kc705: clean up crg namespace

08:23 <mithro> What is the correct way to instantiate/create a 16k ROM block in migen/misoc?

08:26 <sb0> create a memory, and then a port with write_capable=False

08:26 <sb0> the memory takes a init parameter

08:37 <sb0> now *bitgen* tells me I have to connect CE and CLR on the BUFR (yes, clock enable and reset), after the whole synthesis...

08:37 <sb0> business as usual

08:38 <sb0> you'd think it could do CE=1 and CLR=0 by default, which is usually what you do for a clock divider, but no, that would be user-friendly

09:00 <sb0> oh god, it worked

09:01 <GitHub17> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vEHCD

09:01 <GitHub17> artiq/master 04b0db1 Sebastien Bourdeauducq: targets/kc705: pre-divide input RTIO clock to improve non-50% duty cycle tolerance

09:20 <bb-m-labs> build #63 of artiq is complete: Failure [failed lit_test] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq/builds/63

09:39 <sb0> grmbl

09:39 <sb0> whitequark, ^