sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub77> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vEhfj
<GitHub77> artiq/master 17802d3 Sebastien Bourdeauducq: test/coredevice/primes: keep output list entirely on the host
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<bb-m-labs> build #67 of artiq is complete: Failure [failed lit_test] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq/builds/67
<whitequark> let me fix this
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<whitequark> hrm
<GitHub80> [artiq] whitequark pushed 1 new commit to master: http://git.io/vEjnx
<GitHub80> artiq/master 9ed6b54 whitequark: transforms.cfg_simplifier: remove....
<bb-m-labs> build #68 of artiq is complete: Success [build successful] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq/builds/68
<whitequark> \o/ sb0 ^
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<whitequark> sb0: there is a problem with exceptions
<whitequark> sure, I can map exceptions back to something else than ARTIQException, but then you will lose the core device traceback
<whitequark> ah no wait, I can use the same hack as now, though it's gross
<whitequark> sb0: ping
<sb0> whitequark, yes?
<whitequark> I think I told you before that to make an exception recognizable after going through the core device you have to add a builtin
<whitequark> which is incorrect, of course, it just has to derive from ARTIQException
<whitequark> is that still a problem?
<sb0> I'd say no for now, as there are more pressing issues
<whitequark> I kinda started working on it already, so would you figure out if this is the semantics you want or not?
<whitequark> there are some advantages to it, for example, I have to store the core device backtrace and params somewhere
<whitequark> and if I just map it to bare Python exceptions I have to stash them into strings
<whitequark> even if I leave the original around this messes with anything that wants to examine them
<sb0> so you are proposing that all exceptions that go through the core device need to derive from ARTIQException?
<whitequark> in short, yes
<sb0> what if e.g. a RPC raises TypeError?
<whitequark> it will be reraised as an ARTIQException
<whitequark> and you will get one line of backtrace before it went through the core device, as opposed to zero
<whitequark> it's not possible to fake backtraces in python. I tried basically every imaginable option
<sb0> I don't like ARTIQException. can't you catch the exception in the RPC handler, store its class in a map of exceptions that the core device may potentially raise, and raise the correct one?
<sb0> didn't we talk about fake backtraces sometime ago?
<sb0> some templating engine did that iirc
<sb0> ...of course, all this is orders of magnitude less important than e.g. the context managers not working
<whitequark> yes, it used the C bindings to Python to manipulate exceptions
<whitequark> poking the innards of the runtime basically
<sb0> ok, why can't we recycle that?
<whitequark> because it's going to break when a new Python version comes out someday?
<sb0> what was that templating engine again?
<sb0> do they have a good track record of dealing with that?
<sb0> looks acceptable to me. also it seems to be a quite popular project...
<whitequark> "def _init_ugly_crap():" looks acceptable to you? high standards for sure
<whitequark> hm, now that I think about it, it doesn't really matter, because there is an issue that mirrors this
<whitequark> which is, you can't catch a host exception on core device properly. and it can't be solved using this hack
<sb0> why not?
<sb0> the main problem seemed 2 to 3
<whitequark> because right now, only the exception name is put into the core device exception
<sb0> and i've seen plenty of worse code that didn't call itself "ugly crap"
<whitequark> so there's no 1:1 mapping from host exceptions to exceptions on core device
<whitequark> this causes both problems
<whitequark> ARTIQException solved that by having an 1:1 mapping from core device exceptions to ARTIQExceptions
<sb0> i'd say keep ARTIQException for now. sounds like the user-friendlier way would take too much time anyway
<sb0> we can revisit later
<bb-m-labs> build #69 of artiq is complete: Failure [failed anaconda_upload] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq/builds/69
<sb0> fuck
<sb0> ah, nothing serious in fact.
<whitequark> sb0: artiq_corelog hangs right now
<whitequark> why?
<whitequark> "No route to host" 192.168.1.50 actually
<sb0> whitequark, i just checked that the "external clock not present" detection works
<sb0> it did report correctly that the clock was not there, i wonder if that crashed it too
<sb0> let me try again
<sb0> hmm, even after resetting the fpga the board won't come back up
<sb0> fuck
<sb0> the fpga answers jtag though
<whitequark> can you revert it back so i can test my code?
<sb0> i loaded the fpga from jtag (not flash) - and it came back up
<sb0> and i just tried a failed clock switch, and it didn't crash...
<whitequark> hrm
<whitequark> maybe my code crashes it?
<whitequark> yes, yes it does
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<whitequark> wtf
<sb0> fpga reset brought it back up this time
<whitequark> no luck getting the corelog out?..
<whitequark> can you poke memory using jtag maybe?
<sb0> maybe you crashed it while i was attempting to connect...
<sb0> corelog works here
<sb0> you can also look at the serial port if your code crashes lwip
<whitequark> well, it's empty now.
<whitequark> how do I look at the serial port?
<sb0> flterm --port /dev/ttyUSB2
<whitequark> hm, almost works
<whitequark> lwip explodes before I get the entire log on serial
<whitequark> how do you reset the FPGA?
<sb0> there are "load" and "reload" scripts in my home
<sb0> reload reads from flash
<whitequark> ok, that worked
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<whitequark> sb0: how do you reflash?
<GitHub98> [artiq] whitequark pushed 1 new commit to master: http://git.io/vEjHT
<GitHub98> artiq/master 0b69e48 whitequark: transforms.llvm_ir_generator: compare exn typeinfo using strcmp....
<sb0> artiq_flash.sh... or you can take care of #103
<sb0> note that I didn't try flashing with openocd, only loading/resetting
<whitequark> sigh
<whitequark> sb0: can you please reflash runtime?
<whitequark> I've built the package
<sb0> what doesn't work?
<whitequark> hm?
<sb0> 0.0-py_2331+git9ed6b54?
<sb0> whitequark, ^
<whitequark> git0b69e488, it should be
<sb0> where is the package?
<sb0> ah. but the conda dependencies cause issue.
<whitequark> oh
<sb0> let me rebuild the python package
<whitequark> I already did
<bb-m-labs> build #71 of artiq is complete: Exception [exception interrupted] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq/builds/71
<bb-m-labs> build #70 of artiq is complete: Success [build successful] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq/builds/70
<sb0> flashing...
<sb0> btw you can load the runtime with flterm too
<whitequark> oh?
<whitequark> also on kc705?
<sb0> yes, it's the same BIOS
<sb0> and there's TFTP netboot even
<sb0> isn't this linking mechanism incompatible with the MPU proposal?
<whitequark> hm, it would be enough to guard writes, really
<whitequark> since the only thing we really care about are stack overflows, also maybe random unsoundness
<whitequark> hang on
<whitequark> why would it be incompatible? ksupport has a copy of all basic routines
<sb0> but e.g. strcmp is linked with the main binary, ksupport.c is compiled with it, and therefore &strcmp will point to the function in the main binary
<sb0> no?
<sb0> remember there was this problem that the main binary would not know where the functions were in ksupport, and you didn't like my elftools-based script, so you replaced that with a single symbol space
<sb0> board is reflashed and up
<whitequark> thanks
<whitequark> as for ksupport, no
<whitequark> or1k-linux-nm /tmp/kc705/software/runtime/ksupport.elf |grep strcmp
<whitequark> 40404464 T strcmp
<sb0> is it the kernel CPU doing the linking now?
<whitequark> yep
<sb0> ah, ok
<whitequark> I don't remember why exactly I made it so but there was a reason
<whitequark> yeah, you could also guard reads, to catch bugs earlier
<whitequark> ... wtf
<whitequark> it doesn't crash anymore
<whitequark> I didn't do anything that would have made it not crash
<whitequark> .... oh
<whitequark> it was a completely unrelated bug in the unwinder debug logging code which no one has noticed until now by sheer chance
<sb0> how fast is the linker? or is there still a way to load multiple kernels in advance and switch fast between them, e.g. by having a single copy of ksupport?
<whitequark> the linker should take no more than a millisecond to run
<sb0> actually if we do that, the MPU should probably be smarter as well
<whitequark> loading multiple kernels in advance should be easy
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<whitequark> sb0: got kicked out... linode having connectivity issues again
<sb0> ok, nothing happened while you were gone
<whitequark> so, multiple kernels, you literally just load multiple kernels
<whitequark> since they're now PIC
<whitequark> but that's semantically unsound
<whitequark> because kernels carry the state of host objects with them.
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<whitequark> perhaps, but you have to multiplex stuff on commcpu and also give them separate stack spaces
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<GitHub78> [artiq] whitequark pushed 1 new commit to master: http://git.io/vuesC
<GitHub78> artiq/master a2618f0 whitequark: runtime/artiq_personality.c: add missing cast.
<bb-m-labs> build #73 of artiq is complete: Failure [failed lit_test] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq/builds/73
<GitHub70> artiq/master cb90bf6 whitequark: test/coredevice/portability: keep trace list entirely on host.
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<GitHub70> [artiq] whitequark pushed 1 new commit to master: http://git.io/vuesp
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<sb0> Boost GDP—Hyper-personalized advertising, based on quantum computation, will stimulate consumer spending.
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<whitequark> I think I figured out why it crashes
<whitequark> that debug print sometimes causes an unaligned access, which raises an exception, which causes a double fault
<whitequark> what does OR1K do during double fault?
<sb0> stekern, ^
<GitHub153> [artiq] whitequark pushed 3 new commits to master: http://git.io/vueW6
<GitHub153> artiq/master 71d8cbb whitequark: runtime/artiq_personality: add missing cast.
<GitHub153> artiq/master 79d020d whitequark: transforms.artiq_ir_generator: handle terminated try body.
<GitHub153> artiq/master ff0ab73 whitequark: Commit missing parts of 8aa34ee9.
<bb-m-labs> build #74 of artiq is complete: Failure [failed lit_test] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq/builds/74
<GitHub147> [artiq] whitequark pushed 1 new commit to master: http://git.io/vuelL
<GitHub147> artiq/master 693a364 whitequark: transforms.artiq_ir_generator: fix typo.
<GitHub17> [artiq] whitequark pushed 1 new commit to master: http://git.io/vue86
<GitHub17> artiq/master 05bdd5c whitequark: Commit missing parts of 8aa34ee9.
<bb-m-labs> build #45 of artiq-kc705-nist_qc1 is complete: Exception [exception interrupted] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq-kc705-nist_qc1/builds/45
<bb-m-labs> build #75 of artiq is complete: Success [build successful] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq/builds/75
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<bb-m-labs> build #46 of artiq-kc705-nist_qc1 is complete: Success [build successful] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq-kc705-nist_qc1/builds/46
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<whitequark> ok that was easy enough to fix, at least
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<GitHub170> [conda-recipes] whitequark pushed 1 new commit to master: https://github.com/m-labs/conda-recipes/commit/a62e03411ef9758bbd9ee5a1964a7609e9ec42ed
<GitHub170> conda-recipes/master a62e034 whitequark: llvm-or1k: bump.
<whitequark> sb0: WTF
<whitequark> so I just looked up and apparently the machine code I generated for finally: was *never* valid
<whitequark> specifically it did stuff like
<whitequark> l.movhir3, (.Ltmp17+1)
<whitequark> l.orir18, r3, (.Ltmp17+1)
<whitequark> and then it jumped to r3.
<whitequark> how on earth this succeeded?!
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<whitequark> ok, all the rest that's broken is in unittests is 1) resync of attributes and 2) test_loopback_count
<whitequark> sb0, would you look at how we can deal with that test?
<whitequark> sb0: speaking of resync of attributes, I'm not quite sure what's the best implementation strategy
<whitequark> I think they should be sent using an asynchronous (fire-and-forget)[4~ RPC mechanism
<whitequark> furthermore, there is generally a large amount of attributes in any given ARTIQ Python executable, most of which are never modified
<whitequark> furthermore, there are obvious correctness concerns with the host code reading stale data if it's called from an RPC
<whitequark> I suggest sending a fire-and-forget RPC /every time/ an attribute is modified
<whitequark> this solves the problem that most attributes are never modified but still have to be written back
<whitequark> and the correctness issue
<whitequark> it doesn't introduce any more latency than the time needed to serialize an object, unless your buffer is full
<whitequark> it will be slow if you modify a very large array in a loop, but I think we can tell people to just not do that
<whitequark> I can also make a warning for it fairly easily, e.g. one that fires if you modify a list over 100 elements or something
<whitequark> objections?
* whitequark → zzz
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