sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<mithro> sb0: is there a spartan 6 SPI flash proxy compatible with OpenOCD around somewhere?
<mithro> Ahh - looks like I can use https://github.com/jordens/bscan_spi_bitstreams ...
<sb0> yes
<mithro> sb0: They don't appear to be linked from the misoc README, so took me a while to find them. Do you think it is worth adding it there?
<mithro> rjo: ping? - Why doesn't the package matter in your bscan_spi stuff?
<sb0> mithro, migen/misoc/artiq flashing support needs some overhaul. switch to openocd, remove any inferior flasher superseded by it, update the documentation
<mithro> rjo: Your bscan_spi seems to work on my fgg484-3 part - yet on that part T13 is a VCC pins rather than one of the SPI config pins. Is there some special magic which maps from the csg324-2?
<sb0> mithro, i would think the silicon die is the same in all package variants of a given fpga
<sb0> and the bitstreams refer to a given location on the die, not on the package. and the SPI pins have special function, as they are also used for configuration from the flash
* mithro is trying to modify the flash stream to toggle a LED at the same time - slowly getting there
<sb0> mithro, the problem with toggling LEDs is it is board-dependent
<mithro> sb0: yeah - this flash proxy will be specific to my board
<sb0> why not use a generic flash proxy that will work on all boards with that FPGA?
<sb0> in fact, they should work on all boards with the same FPGA die, if we make some assumptions that are actually reasonable
<mithro> sb0: because this board has an error on it (fixed on prod boards) which means if you pull a given pin low it resets the USB JTAG programming chip
<mithro> sb0: so once I have a custom flash proxy, making it flash an LED so I can see what is going on seems like a simple thing to do
<mithro> sb0: actually adding a "-g UnusedPin=PullNone" to the bitstream generation would make the generic flash proxy work on this board
<sb0> mithro, i'd recommend that...
<mithro> sb0: I'll send a pull request with that
<mithro> sb0: I'd be skeptical that anything from Xilinx is reasonable ;)
<GitHub104> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vEJ0h
<GitHub104> artiq/master 46f59b6 Sebastien Bourdeauducq: coredevice: analyzer message decoding
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<whitequark> sb0: fixed (I think)
<GitHub109> [artiq] whitequark pushed 1 new commit to master: http://git.io/vEJAt
<GitHub109> artiq/master e4615e7 whitequark: transforms.int_monomorphizer: visit children of CallT.
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<GitHub192> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vEUGy
<GitHub192> artiq/master cdcb57e Sebastien Bourdeauducq: coredevice/analyzer: basic VCD writing
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<GitHub28> [artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/vEUHb
<GitHub28> artiq/master b96e0d2 Sebastien Bourdeauducq: coredevice/analyzer: set VCD timescale
<GitHub28> artiq/master 4b5c10b Sebastien Bourdeauducq: coredevice/core: remove default period
<GitHub103> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vEU7L
<GitHub103> artiq/master 5769107 Sebastien Bourdeauducq: gateware/rtio: keep counter clock domain transfer active during CSR reset
<bb-m-labs> build #23 of artiq-kc705-nist_qc1 is complete: Failure [failed conda_build] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq-kc705-nist_qc1/builds/23
<bb-m-labs> build #51 of artiq is complete: Failure [failed conda_build] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq/builds/51
<bb-m-labs> build #24 of artiq-kc705-nist_qc1 is complete: Failure [failed conda_build] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq-kc705-nist_qc1/builds/24
<bb-m-labs> build #52 of artiq is complete: Failure [failed conda_build] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq/builds/52
<sb0> whitequark, do you know what is going on?
<sb0> rjo, how should a dds channel be displayed in the vcd?
<GitHub172> [artiq] sbourdeauducq pushed 3 new commits to master: http://git.io/vETT3
<GitHub172> artiq/master a26ffc5 Sebastien Bourdeauducq: setup.py: use consistent interpreter
<GitHub172> artiq/master 2ae6357 Sebastien Bourdeauducq: frontend/coretool: verbosity control
<GitHub172> artiq/master 183e855 Sebastien Bourdeauducq: remove workaround_asyncio263
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<whitequark> sb0: let me see
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<bb-m-labs> build #53 of artiq is complete: Failure [failed lit_test] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq/builds/53
<whitequark> sb0: that breakage was caused by the continuum.io proxy malfunctioning