sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> whitequark, seems the dds amplitude support didn't make the compiler merge either...
<GitHub11> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vEl48
<GitHub11> artiq/master e4d73c0 Sebastien Bourdeauducq: artiq/coredevice/dds: fix dds_set signature
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<bb-m-labs> build #30 of artiq-kc705-nist_qc1 is complete: Success [build successful] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq-kc705-nist_qc1/builds/30
<bb-m-labs> build #22 of artiq-kc705-nist_qc2 is complete: Success [build successful] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq-kc705-nist_qc2/builds/22
<bb-m-labs> build #20 of artiq-pipistrello-nist_qc1 is complete: Success [build successful] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq-pipistrello-nist_qc1/builds/20
<GitHub44> [artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/vElHb
<GitHub44> artiq/master 58d0e2c Sebastien Bourdeauducq: coredevice/analyzer: log TTL decoding in debug mode
<GitHub44> artiq/master 4be5df9 Sebastien Bourdeauducq: coredevice/analyzer: DDS decoding
<sb0> whitequark, you connected user_gpio_n to user_clk_p
<sb0> user_clk_{p,n} is used to receive a differential clock for phase-locking RTIO: https://github.com/m-labs/artiq/blob/master/artiq/gateware/targets/kc705.py#L42
<sb0> user_gpio_n is a single-ended TTL output, driven by the RTIO core (that requires clocking): https://github.com/m-labs/artiq/blob/master/artiq/gateware/targets/kc705.py#L168
<sb0> this connection makes no sense at all
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<sb0> whitequark, are you allowed to create user classes on the device?
<sb0> *instances of
<sb0> it doesn't reject the instance creation, but then all attributes/methods are not found
<sb0> it's fine if it doesn't work, just wondering...
<whitequark> sb0: oh, it is a clock INPUT
<whitequark> that makes total sense, unfortunately
<whitequark> so where the hell is the clock output?
<whitequark> as for user classes, it's a bit tricky
<whitequark> the immediate reason it doesn't work is that ARTIQ Python does not really implement constructors
<whitequark> the reason you can create an instance is basically by accident; you shouldn't really
<whitequark> shouldn't be able to.
<whitequark> but the real reason it's not implemented is that we do not currently have a way to serialize newly created user classes
<sb0> the 10MHz clock output is on user_gpio_p
<sb0> the configurable clock generator is somewhere on the FMC
<sb0> user_gpio_n can be used as input as well btw (controllable dynamically from kernels)
<whitequark> ohh
<whitequark> ok, so would you connect them?
<sb0> ideally you'd feed 1MHz, not 10
<sb0> 10 will cause overflows with large lists, as the cpu won't keep up
<sb0> btw, it's outputting 10MHz to drive the SynthNV PLL, which can be used to clock DDSes
<sb0> and that 10MHz is phase-locked to whatever the RTIO clock is
<sb0> the debug setup is onboard oscillator -> RTIO + 10MHz -> SynthNV -> DDS
<whitequark> ok
<whitequark> that's not really very relevant for now anyway...
<sb0> the lab setup is expensive oscillator -> DDSes + user_clock_{n,p}
<sb0> no, just explaining why things are like that
<whitequark> oh i see your point now
<sb0> they even put that MIPI connector on it?
<whitequark> where?
<whitequark> none of those look like MIPI to me... one contact row
<sb0> "MIPI DSI and CSI-2 connectors"
<whitequark> oh
<sb0> are those standard docs still expensive btw?
<whitequark> oh, camera and display, I see, I thought you meant the debug ones
<whitequark> I think so, yes
<whitequark> rpi has dsi and csi, too
<sb0> yeah, 2k USD/month minimum
<whitequark> someone should pirate those
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<felix_> at least some older version of the mipi specs float around somewhere on the net
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<cyrozap> whitequark, sb0, felix_: http://electricstuff.co.uk/nanohack.html
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<aeris> https://youtu.be/FLqo0pmptsE ça à l'air sympa par chez vous...
<whitequark> very nice hack
<aeris> miss, sorry :x
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