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sb0 >
rjo, it works when using your script
02:39
<
sb0 >
rjo, the error I mentioned is when using the supplied digilent-hs1 script + transport jtag + adapter_khz
02:39
<
sb0 >
rjo, does the "pld init" command work? it says init must be used before it, even though i did...
03:06
<
rjo >
could you paste what you did somewhere?
03:10
<
rjo >
did you do "pld init" before "jtag newtap ..." and "pld device ..."?
03:11
<
sb0 >
let me try pld init again...
03:11
<
rjo >
i can't find pld init anywhere in the docs
03:12
<
rjo >
your script is pretty short. looks like autodetecting irlen etc failed. no idea what would need to be done to make that work.
03:13
<
sb0 >
it works with the following script:
03:13
<
sb0 >
source [find interface/ftdi/digilent-hs1.cfg]
03:13
<
sb0 >
source [find cpld/xilinx-xc7.cfg]
03:13
<
sb0 >
source [find cpld/jtagspi.cfg]
03:13
<
sb0 >
adapter_khz 25000
03:13
<
sb0 >
and now with that script that works
03:14
<
rjo >
yes. there are a bunch of things in xilinx-xc7.cfg that do the right thing.
03:15
<
sb0 >
I think pld init is supposed to trigger a reconfiguration of the device, i.e. reboot with the bitstream from flash
03:15
<
rjo >
to me, jtag never looked like something where you could do a lot of autodetection.
03:15
<
rjo >
xc7_program does that.
03:17
<
sb0 >
ah, yes, "xc7_program xc7.tap" worked. thanks!
03:19
<
sb0 >
there is also no reset bug anymore (i was loading the bitstream through jtag to reboot the board before, which is broken with xc3sprog...)
03:21
<
rjo >
yep. its pretty nice. the biggest time consumption is writing the runtime to flash
03:22
<
rjo >
i don't think pld init does anything useful. at least from looking at the code.
03:28
<
sb0 >
you can netboot the runtime ...
03:31
<
sb0 >
flterm loading also works, but is slow as well
03:32
<
rjo >
can one actually expect that the bios will not need reflashing "most of the time"?
03:32
<
rjo >
for reasonably intrusive work on the gateware where the relevant csrs and irqs don't move around...
03:32
<
sb0 >
or the BIOS can be embedded, which is not a problem on the monster-board that has a lot of block RAM
03:34
<
sb0 >
build with --integrated-rom-size
03:35
<
rjo >
good god is this network bad again. i don't see how irc can work so well when http and ssh are constantly crapping out. what do you do if the ping RTT to your DNS server down the hallway is 50 ms? you go home.
03:35
<
rjo >
yep. that and netboot would probably be the way to go for CI hardware testing then.
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rjo >
damn even things like level 3 are actually based here...
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07:11
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sb0 >
whitequark, ^
07:13
<
whitequark >
ah I recall that
07:17
<
GitHub134 >
artiq/master 40e10ca Sebastien Bourdeauducq: examples/blink_forever: revert incorrectly committed changes
07:17
<
GitHub134 >
artiq/master f431add Sebastien Bourdeauducq: runtime/analyzer: fix zero data corner case, handle cache
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GitHub138 >
artiq/master 59a3ea4 Sebastien Bourdeauducq: gateware/rtio/analyzer: fix bus write
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whitequark >
hm, that was tricker than I expected
08:40
<
GitHub135 >
artiq/master 3fbee27 whitequark: analyses.domination: consider unreachable blocks dominated by any other....
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09:25
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whitequark >
sb0: how do you enable logging in comm_generic?
09:26
<
whitequark >
logger.setLevel(logging.DEBUG) doesn't work
09:26
<
sb0 >
logging.setLevel?
09:26
<
sb0 >
er, no, it's basicConfig
09:27
<
sb0 >
or use -v -v in the tool you're using
09:27
<
whitequark >
it's unit test, not a tool
09:29
<
whitequark >
should it be possible to get a return value from an initially invoked kernel?
09:40
<
sb0 >
cool, the analyzer core is working
09:40
<
sb0 >
the only bug i see so far is the exception rtio_counter is borked (shifted by 20-something bits) for some reason...
09:46
<
whitequark >
analyzer?
09:46
<
whitequark >
logic?
09:58
<
sb0 >
rtio activity dumper, yes
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10:03
<
GitHub101 >
artiq/master f4b19fe whitequark: compiler.types: make TValue hashable.
10:03
<
GitHub101 >
artiq/master 52102a1 whitequark: Fix handling of default values for RPC arguments (fixes #190).
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10:23
<
GitHub78 >
artiq/master 10d4bfb Sebastien Bourdeauducq: frontend/coretool: basic analyzer dump
10:23
<
GitHub78 >
artiq/master 0832c71 Sebastien Bourdeauducq: coredevice/comm_tcp: support retrieving analyzer data
10:25
<
sb0 >
oh, i found the bug. it was silly.
10:27
<
GitHub59 >
artiq/master 64ad388 Sebastien Bourdeauducq: gateware/rtio/analyzer: fix exception message layout
10:32
<
sb0 >
whitequark, so you could use artiq_coretool.py analyzer-dump to see what your kernels are doing now =]
10:33
<
sb0 >
the python part is just a quick hack right now, will have to think about how to format a nice VCD
10:36
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whitequark >
i'll try it once i get there
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10:41
<
sb0 >
the device records all the time to a SDRAM ringbuffer, and analyzer-dump reads out that buffer and clears it
10:43
<
sb0 >
rjo, how large should the buffer be?
10:46
<
sb0 >
whitequark, are you using the fact that artiq.gateware doesn't depend on anything else in artiq?
10:46
<
sb0 >
I need to put the shared constants for the analyzer somewhere
10:47
<
sb0 >
options are duplicate them (there aren't too many), put them in artiq.gateware, or put them in artiq.coredevice
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11:15
<
whitequark >
.gateware, sure
13:03
<
GitHub38 >
artiq/master 2759310 whitequark: transforms.iodelay_estimator: reject control flow in 'with parallel:' (fixes #195).
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GitHub193 >
artiq/master 0755aa3 whitequark: transforms.iodelay_estimator: allow goto in zero-iodelay while statements.
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GitHub92 >
misoc/master a625469 whitequark: libcompiler_rt: include __powidf2.
16:15
<
GitHub89 >
artiq/master 7b3ace2 whitequark: transforms.inferencer: fix unsupported decorator diagnostic when embedding....
16:15
<
GitHub89 >
artiq/master baa986a whitequark: compiler.prelude: add @portable as an alias for @kernel.
16:15
<
GitHub89 >
artiq/master 0395efd whitequark: compiler: give environment types in LLVM IR readable names.
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whitequark >
what the fuck is the problem with it again?
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16:28
<
whitequark >
oh, that's actually my fault.
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19:26
<
rjo >
sb0: one entry at 256 bit? 100k entries would likely be fine and fit pipistrello.
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19:36
<
rjo >
sb0: but if at all possible this should be a ringbuffer that always spans the last 100k event and is also not cleared between experiments. it would basically be always full. whether or not reading it out actually clears it does not matter much to me.
19:37
<
rjo >
and if reading the 100k events takes 10 s thats fine as well.
19:57
<
rjo >
anybody: how would a "correct" spi slave do its deglitching/synchronization?
19:58
<
rjo >
actually clocking it with the spi clk and then CDCing the data seems problematic for several reasons.
20:01
<
rjo >
a few MultiRegs (under the assumption that spi_clk < sys_clk/2) seems correct and easy.
20:05
<
rjo >
ah. no. MultiRegs and and some kind of majority vote.
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20:41
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GitHub60 >
conda-recipes/master c4dc32f whitequark: llvmlite-artiq: bump.
21:26
<
GitHub150 >
artiq/master 4fb1de3 whitequark: Initial invocation of a @kernel function can now return a value (fixes #197).
22:41
<
GitHub33 >
artiq/master 4fcd6ab whitequark: Commit missing parts of 0395efd4.
22:41
<
GitHub33 >
artiq/master afee03b whitequark: Commit missing parts of 4fb1de33.
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