sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0> larsc, lm32?
<sb0> or navre, for something smaller
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<GitHub15> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vE1OX
<GitHub15> artiq/master 70dfad0 Sebastien Bourdeauducq: applets: add XY/histogram plot demo
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<GitHub66> [pythonparser] whitequark pushed 1 new commit to master: http://git.io/vEMCM
<GitHub66> pythonparser/master 58a0c8f whitequark: Clarify license.
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<whitequark> ^ someone wrote me asking whether it was 3-clause BSD or some other BSD, after which I decided not to bother with BSD
<sb0> whitequark, what is your argument for MIT?
<whitequark> sb0: the fact that I don't want anyone, starting with me, to care about what version of BSD it is
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<larsc> sb0: the problem with lm32 is, as you well know, that the toolchain breaks every so often
<sb0> larsc, then use navre or stick to a known-good version
<larsc> no openrisc?
<kristianpaul> larsc: what about picorv32?
<whitequark> oh dear
<kristianpaul> what did i said? :p
<sb0> openrisc also has toolchain issues
<sb0> not as bad as lm32, but still
<kristianpaul> well...
<sb0> i think Tomasz Wlostowski made a small riscv implementation; not sure how good it is nor if the toolchain works
<sb0> whitequark, can you clarify what "storage for static experiments" is?
<whitequark> sb0: me?
<sb0> it's part of core device storage. yes, post on the ML
<whitequark> ah, in that sense. yes
<sb0> i guess the rest should be simply a) upload kernels in several packets (so we meet the 10MB/item spec) b) some global key/value store accessible from kernels, possibly as simple as a linked list using the lwip malloc and managed by the comms-cpu
<whitequark> we don't need a), it's enough to call a host RPC that returns the large string
<whitequark> since there are no limits on that
<whitequark> as for b) I think that will conflict with the rudimentary MPU proposal
<whitequark> not sure what can be done about that
<sb0> put the key/value malloc area into kernel-cpu-dedicated memory space
<sb0> i think lwip supports defining several malloc areas...
<whitequark> ah yes, that would work
<sb0> no limits on host RPC data sizes? so packet-splitting is implemented for those?
<whitequark> oh.
<whitequark> oh right, same problem.
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<GitHub186> [artiq] whitequark pushed 3 new commits to master: http://git.io/vEyYt
<GitHub186> artiq/master 57ebd57 whitequark: transforms.dead_code_eliminator: update doc.
<GitHub186> artiq/master 8822db0 whitequark: transforms.cfg_simplifier: implement....
<GitHub186> artiq/master db05ec0 whitequark: test.coredevice.portability.HostVsDeviceCase.test_misc: update....
<whitequark> test_pulses is actually broken on /host/
<whitequark> sb0: could you take a look at that one? it's very strange
<GitHub166> [artiq] whitequark pushed 2 new commits to master: http://git.io/vEyBG
<GitHub166> artiq/master 0dd7194 whitequark: test.coredevice.portability.HostVsDeviceCase.test_exceptions: update....
<GitHub166> artiq/master 8fb6d4c whitequark: coredevice.comm_generic: handle RPC default args correctly.
<GitHub110> [artiq] whitequark pushed 1 new commit to master: http://git.io/vEyEg
<GitHub110> artiq/master 9d7d614 whitequark: test.coredevice.rtio.CoredeviceTest.test_time_keeps_running: relax timing....
<whitequark> ok, I've summarized remaining bugs in https://github.com/m-labs/artiq/issues/177
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