sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<bb-m-labs> build #25 of artiq-kc705-nist_qc1 is complete: Failure [failed anaconda_upload] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq-kc705-nist_qc1/builds/25
<bb-m-labs> build #54 of artiq is complete: Success [build successful] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq/builds/54
rohitksingh has quit [Quit: Leaving.]
bb-m-labs has quit [Quit: buildmaster reconfigured: bot disconnecting]
bb-m-labs has joined #m-labs
bb-m-labs has quit [Client Quit]
bb-m-labs has joined #m-labs
bb-m-labs has quit [Quit: buildmaster reconfigured: bot disconnecting]
bb-m-labs has joined #m-labs
bb-m-labs has quit [Client Quit]
bb-m-labs has joined #m-labs
bb-m-labs has quit [Quit: buildmaster reconfigured: bot disconnecting]
bb-m-labs has joined #m-labs
<whitequark> and *that* breakage was caused by the same bug as the one which broke our travis
<whitequark> i now added a step which will abort the build and let me investigate why the fuck that happens, next time it does
fengling has joined #m-labs
rjo_ has joined #m-labs
<rjo_> mithro: its the same chip, independent of the package.
fengling has quit [Ping timeout: 256 seconds]
<rjo_> mithro: if you generate for different packages you get the same bitstream.
fengling has joined #m-labs
<GitHub19> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vEIy8
<GitHub19> artiq/master e87436f Sebastien Bourdeauducq: coredevice/analyzer: remove zero-timestamp msg filtering (now unnecessary)
<rjo_> sb0: if it is easy given the dds shared bus and the splitting of the registers, represent a dds channel as one signal for frequency and one for phase. you probably want to ignore the distiction of the different interpretations of phase and just take the POW.
<rjo_> sb0: i think we might want a 0th order default handler that just takes rtio data verbatim.
fengling has quit [Ping timeout: 256 seconds]
fengling has joined #m-labs
<rjo_> sb0: "timestamp" is the timestamp of the event, right? that coincides with now_mu() for outputs. for input events it doesn't. then you don't know when a given input event was actually read. but that might be fine, just pointing it out because it can make debugging a bit harder if an input event was the cause of something else.
<rjo_> sb0: afaict the analyzer is only accessible through the netserver currently. if i wanted to freeze the analyzer from a kernel (because i detected an abnormal situation), would i just throw an exception and then hope nobody executes another kernel that continues filling the analyzer?
<sb0> rjo_, yes, that dds handling is possible (with the first values possibly undefined as the relevant writes may have been pushed out of the ringbuffer, but that's a general problem which is only particularly present here)
<rjo_> sb0: all channels will have unknown values initially until they are written the first time, right?
<sb0> for inputs, unless there's a bug, timestamp is when the signal changed state, and rtio_counter is when it is read
<sb0> as for freezing: yes (or that the new kernel does not fill the analyzer buffer)
<rjo_> when do you let an input channel, where you only trigger rising, fall?
<rjo_> sb0: but don't we usually return to the idle kernel and that can fill the buffer pretty quickly?
<rjo_> could we either have the comms cpu intercept a special FreezeAnalyzer Exception or give ksupport to the kernel for controlling the analyzer?
<sb0> what about having the kernel call a RPC on the host that doesn't return until some user action?
<rjo_> sb0: for inputs it should probably fine to only have rtio_counter and timestamp. even if the third time, now_mu(), is different and might be relevant.
<rjo_> then the kernel can just rpc the readout of the buffer.
<sb0> I guess that works, and doesn't create much spaghetti in the runtime
<rjo_> ack. let's take that as the comme il faut
<rjo_> sb0: in misoc.stream with packetized, is the notion generally that sop/eop are valid during stb?
<sb0> I asked _florent_ that question a few months ago but cannot find it in the irc log right now...
<rjo_> seems to me that just eop would have been sufficient.
<sb0> yes, i was also using a single-signal protocol for the framebuffer and dvi in mixxeo... _florent_ why did you add another one?
<GitHub160> [migen] jordens pushed 1 new commit to master: http://git.io/vELLl
<GitHub160> migen/master 1c30796 Robert Jordens: sim: support evaluating Replicate()
<rjo_> sb0: shouldn't Simulator() do a _lower_specials() sweep (from fhdl.verilog)? otherwise e.g. the default imeplementation of MultiReg gets lost.
<rjo_> ... and then also at least warn that there are specials left
<sb0> rjo_, yes, it should, there's an issue about that
<sb0> haven't looked into it yet
<rjo_> sb0: doing it (exact same code as from verilog) fixes that.
<rjo_> but i am seeing another issue somewhere else still...
rjo_ has quit [Ping timeout: 246 seconds]
siruf_ has joined #m-labs
jaeckel has quit [*.net *.split]
siruf has quit [*.net *.split]
siruf_ is now known as siruf
jaeckel has joined #m-labs
fengling has quit [Ping timeout: 256 seconds]
balrog_ has joined #m-labs
jaeckel_ has joined #m-labs
jaeckel has quit [*.net *.split]
balrog has quit [*.net *.split]
balrog_ is now known as balrog
jaeckel_ is now known as jaeckel
fengling has joined #m-labs
fengling has quit [Quit: WeeChat 1.2]
<GitHub106> [artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/vEtm9
<GitHub106> artiq/master 8691f69 Sebastien Bourdeauducq: gateware/rtio/analyzer: suppress spurious initial reset messages
<GitHub106> artiq/master 007a717 Sebastien Bourdeauducq: analyzer: report DDS channel number
<sb0> whitequark, been thinking the "displays" should not be called displays, as the embedded programs could be used for other things as well ...
<GitHub14> [artiq] whitequark pushed 1 new commit to master: http://git.io/vEqvy
<GitHub14> artiq/master f957be4 whitequark: transforms.llvm_ir_generator: handle loop instruction (fixes #202).
rohitksingh has joined #m-labs
<GitHub76> [artiq] whitequark pushed 2 new commits to master: http://git.io/vEqLR
<GitHub76> artiq/master 25188f0 whitequark: transforms.interleaver: correctly handle degenerate `with parallel:` blocks.
<GitHub76> artiq/master ac5c86b whitequark: artiq_compile: add missing import.
<cr1901_modern> whitequark: Is it an analog or digital PID controller. If the former, I can run some tests to help you decide the params
<bb-m-labs> build #29 of misoc is complete: Failure [failed anaconda_upload] Build details are at http://m-labs-buildserver.lan/buildbot/builders/misoc/builds/29
<bb-m-labs> build #29 of artiq-kc705-nist_qc1 is complete: Exception [exception interrupted] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq-kc705-nist_qc1/builds/29
<bb-m-labs> build #21 of artiq-kc705-nist_qc2 is complete: Exception [exception interrupted] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq-kc705-nist_qc2/builds/21
<bb-m-labs> build #19 of artiq-pipistrello-nist_qc1 is complete: Exception [exception interrupted] Build details are at http://m-labs-buildserver.lan/buildbot/builders/artiq-pipistrello-nist_qc1/builds/19
ylamarre has joined #m-labs
<whitequark> cr1901_modern: what?
ylamarre has quit [Quit: ylamarre]
<_florent_> sb0: you were using sof in dvi, AXI is using tlast, we can generally only have one delimiter and deduce the other, but I find code easier to understand and simulate with both
<rjo> sb0 or _florent_ (anybody with a kc705 around and about to workd with it using openocd): could you give this new bitstream a spin: https://github.com/jordens/bscan_spi_bitstreams
<rjo> _florent_: but this putative convenience comes at a cost: what is supposed to happen if the sequencing is violated (eop before sop)? or what does stb before sop do?
<_florent_> yes, in that case you can discard, I use this because this was close to Avalon ST
<_florent_> but maybe we should use a standardized streaming bus: AXI or Avalon ST
<rjo> AXI looks obscene. AFAICT most people just convert it to something simpler: https://github.com/jordens/redpid/blob/master/verilog/axi_slave.v