00:52 <sb0> whitequark, the priority is to get the current features implemented, so we can do this extremely late merge. you can fix this sort of detail later.

04:40 <cr1901_modern1> whitequark: I don't actually have a supply w/ a constant current mode, but now that you mention it... doesn't really stop me from making a simple one with a BJT and zener diode.

05:17 <rjo> sb0: how do I port TRead, TWrite and Initiator?

05:19 <sb0> rjo, I propose this way instead: https://github.com/m-labs/misoc/blob/master/misoc/interconnect/wishbone.py#L45

05:19 <sb0> https://github.com/m-labs/artiq/blob/master/artiq/gateware/ad9xxx.py#L158

05:59 <whitequark> sb0: yes but I confused myself while writing some code anyway

06:10 <rjo> sb0: looks good. interfaces know how to generate these compound simulator actions.

06:11 <rjo> sb0: did you think about how to interleave them? if I have two buses driven from one generator...

06:15 <sb0> rjo, you cannot perform the two transactions simultaneously from one generator, but driving them one by one should work just fine

06:16 <rjo> sure.

06:16 <rjo> sb0: will there be read()/write() for csr_bus.Interface?

06:18 <sb0> I haven't written them, but they would be nice to have

14:47 <GitHub61> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/v4W9y

14:47 <GitHub61> artiq/master 723ef71 Sebastien Bourdeauducq: master/repository: fix experiment name conflict handling

15:10 <travis-ci> m-labs/artiq#587 (master - 723ef71 : Sebastien Bourdeauducq): The build has errored.

15:10 <travis-ci> Build details : https://travis-ci.org/m-labs/artiq/builds/91393023

21:02 <GitHub96> [artiq] whitequark pushed 1 new commit to new-py2llvm: http://git.io/v442R

21:02 <GitHub96> artiq/new-py2llvm eefa9e2 whitequark: transforms.inferencer: fix typo.

21:23 <GitHub180> [artiq] whitequark pushed 1 new commit to new-py2llvm: http://git.io/v446A

21:23 <GitHub180> artiq/new-py2llvm fd46690 whitequark: compiler: make IR dumps vastly more readable.

21:52 <GitHub3> [artiq] whitequark pushed 3 new commits to new-py2llvm: http://git.io/v44HF

21:52 <GitHub3> artiq/new-py2llvm 629aace whitequark: compiler.iodelay: add forgotten Conv.__eq__.

21:52 <GitHub3> artiq/new-py2llvm a2d73c8 whitequark: compiler.types: dump type variable iodelay explicitly.

21:52 <GitHub3> artiq/new-py2llvm e67705d whitequark: compiler.iodelay: fix typo in BinOp.__eq__.

22:00 <GitHub58> [artiq] whitequark pushed 4 new commits to new-py2llvm: http://git.io/v44dT

22:00 <GitHub58> artiq/new-py2llvm 841e01a whitequark: compiler.iodelay: fix typo in Var.__eq__.

22:00 <GitHub58> artiq/new-py2llvm 10f82ff whitequark: transforms.iodelay_estimator: do not unify indeterminate delays.

22:00 <GitHub58> artiq/new-py2llvm 44d0a35 whitequark: transforms.iodelay_estimator: actually iterate to fixpoint.

22:04 <GitHub73> [artiq] whitequark pushed 2 new commits to new-py2llvm: http://git.io/v44FX

22:04 <GitHub73> artiq/new-py2llvm 3fb12b7 whitequark: lit-test: update to follow IR serialization changes.

22:04 <GitHub73> artiq/new-py2llvm 80f0bfe whitequark: lit-test: add test for iodelay order invariance.

22:19 <GitHub192> [artiq] whitequark pushed 2 new commits to new-py2llvm: http://git.io/v44jV

22:19 <GitHub192> artiq/new-py2llvm b0c6b70 whitequark: transforms.asttyped_rewriter: fix class redefinition diagnostic.

22:19 <GitHub192> artiq/new-py2llvm 506725f whitequark: transforms.iodelay_estimator: fix handling of methods.

22:23 <GitHub102> [artiq] whitequark pushed 1 new commit to new-py2llvm: http://git.io/v4BvR

22:23 <GitHub102> artiq/new-py2llvm e619154 whitequark: transforms.iodelay_estimator: fix handling of `with sequential`.