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GitHub27>
migen/master e50df16 Sebastien Bourdeauducq: sim: add support for passive generators
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travis-ci>
m-labs/migen#164 (master - e50df16 : Sebastien Bourdeauducq): The build passed.
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GitHub96>
migen/master 1846258 Sebastien Bourdeauducq: sim: deterministic clock iteration
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GitHub96>
migen/master e893f56 Sebastien Bourdeauducq: sim/vcd: support signals not appearing in FHDL
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travis-ci>
m-labs/migen#165 (master - e893f56 : Sebastien Bourdeauducq): The build passed.
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ysionneau>
sb0: can I push the patches I sent on the mailing list or is there something wrong with them?
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sb0>
ysionneau, are they not in the repos yet?
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ysionneau>
ah, let me check
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ysionneau>
ah yes indeed
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ysionneau>
Since I didn't get any ack on the ML I didn't think it was integrated
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sb0>
oh, Serge Haroche is speaking in Hong Kong this week
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sb0>
whitequark, ^+
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GitHub103>
artiq/new-py2llvm c8cfa7c whitequark: compiler: give suggestions in diagnostics for unbound variable....
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whitequark>
cr1901_modern1: you cannot, but you can take your PSU to a constant current mode
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