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<
cyrozap >
Is there a way to find what the output DDR clock phase should be deterministically?
01:50
<
cyrozap >
And also what the read/write bitslip values should be?
01:57
<
sb0 >
cyrozap, there aren't good tools for that
01:58
<
cyrozap >
sb0: Is there a way to manually calculate it?
01:59
<
cyrozap >
How were they figured out for all the other boards?
02:01
<
sb0 >
somewhat empirically. theoretically, there should be a way to calculate it, though it's easy to make mistakes there.
02:05
<
sb0 >
cr1901_modern, pyqtgraph might provide you with some graphics tools you may want to look at...
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cr1901_modern >
sb0: yes, pyqtgraph doesn't completely describe the library; it does have widgets it provides. Not yet sure I can extend them.
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<
cr1901_modern >
I would prefer to keep the amount of custom widget code I have to write to a minimum (just the dual-slider 'number line' with tick marks)
02:20
<
sb0 >
cr1901_modern, what I meant is it has code for drawing axes, cursors, etc.
02:21
<
sb0 >
cr1901_modern, I don't know if it is a good idea to reuse it, but I suggest having a look
02:26
<
sb0 >
_florent_, do you also have a reset bug on misoc new + kc705?
02:26
<
sb0 >
the soc won't boot until you hit the cpu reset button
02:26
<
cr1901_modern >
Ahhh, well I'll take a look, if I think it's too limited I'll write my own
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07:01
<
GitHub192 >
migen/new 5c30962 Sebastien Bourdeauducq: build/ise: make method default args consistent across platforms
07:01
<
GitHub192 >
migen/new 56aac31 Sebastien Bourdeauducq: build: standardize toolchain path setting
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travis-ci >
m-labs/migen#154 (new - 56aac31 : Sebastien Bourdeauducq): The build passed.
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<
GitHub121 >
misoc/new 71fd951 Sebastien Bourdeauducq: integration/builder: add gateware toolchain path command line switch
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<
travis-ci >
m-labs/misoc#8 (new - 71fd951 : Sebastien Bourdeauducq): The build passed.
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travis-ci >
m-labs/migen#155 (legacy - a619d37 : whitequark): The build passed.
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08:15
<
GitHub99 >
migen/master ae95256 Sebastien Bourdeauducq: Merge 'new' branch
08:15
<
GitHub99 >
migen/master 046b598 Sebastien Bourdeauducq: conda: use correct branch
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<
travis-ci >
m-labs/migen#156 (master - 046b598 : Sebastien Bourdeauducq): The build passed.
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08:19
<
sb0 >
Auto-merging misoc/cores/lm32/verilog/submodule
08:19
<
sb0 >
Adding as misoc/cores/lm32/verilog/submodule~new instead
08:19
<
sb0 >
sure, fuck it up as usual
08:19
<
sb0 >
do people actually use submodules?
08:19
<
whitequark >
I use submodules all the time
08:20
<
sb0 >
git mv breaks, git merge breaks
08:20
<
whitequark >
I might have run into an obscure bug, maybe, once? ever?
08:20
<
sb0 >
does anything work?
08:20
<
larsc >
git pull works
08:20
<
whitequark >
never tried to mv them
08:21
<
sb0 >
the mv bug is blatant. create a folder A, put a submodule A/B, and then git mv A C
08:21
<
sb0 >
this will bork your .git and require manual edits
08:21
<
whitequark >
yeah, that's idiotic
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08:30
<
sb0 >
$ git add misoc/cores/lm32/verilog/submodule
08:30
<
sb0 >
error: unable to index file misoc/cores/lm32/verilog/submodule
08:30
<
sb0 >
fatal: updating files failed
08:32
<
sb0 >
this is ridiculous as well. move a submodule in a branch, merge that branch, and your git index is broken.
08:33
<
sb0 >
I wonder why git advertises support for submodules at all, if obvious corner cases like this are not supported
08:41
<
sb0 >
the bug also manifests itself if submodules aren't even checked out
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08:47
<
_florent_ >
sb0: concerning the reset on the kc705 I don't remember pressing reset to get it work, so I would say it was working fine
08:48
<
sb0 >
_florent_, in fact the bug is not there when loading from flash... it's an old one i think
08:48
<
_florent_ >
but I was using an internal rom for the bios
08:49
<
GitHub62 >
misoc/master da171d8 Sebastien Bourdeauducq: Merge 'new' branch
08:51
<
sb0 >
whitequark, any reason why migen is a build requirement of artiq? (the non-bitstream package)
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<
travis-ci >
m-labs/misoc#10 (master - da171d8 : Sebastien Bourdeauducq): The build has errored.
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08:52
<
GitHub190 >
misoc/master 1ea775e Sebastien Bourdeauducq: conda: use correct branch
08:52
<
GitHub190 >
misoc/master 2de8e1d Sebastien Bourdeauducq: setup.py: consistent version number
08:53
<
GitHub183 >
misoc/master 1d60882 Sebastien Bourdeauducq: setup.py: fix version number
08:54
<
GitHub50 >
migen/master 180ba95 Sebastien Bourdeauducq: setup.py: consistent version number
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<
travis-ci >
m-labs/misoc#11 (master - 2de8e1d : Sebastien Bourdeauducq): The build passed.
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<
travis-ci >
m-labs/misoc#12 (master - 1d60882 : Sebastien Bourdeauducq): The build passed.
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08:56
<
GitHub148 >
artiq/master 644a410 Sebastien Bourdeauducq: thorlabs_tcube: fix -P case handling
08:56
<
GitHub148 >
artiq/master e26147b Sebastien Bourdeauducq: gateware,runtime: use new migen/misoc
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<
GitHub148 >
artiq/master 3404a65 Sebastien Bourdeauducq: frontend/artiq_flash: reorganize device binaries
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travis-ci >
m-labs/migen#157 (master - 180ba95 : Sebastien Bourdeauducq): The build passed.
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<
travis-ci >
m-labs/artiq#567 (master - 4d0f500 : Sebastien Bourdeauducq): The build was broken.
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<
travis-ci >
m-labs/migen#158 (0.2 - 046b598 : Sebastien Bourdeauducq): The build passed.
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<
travis-ci >
m-labs/migen#157 (master - 180ba95 : Sebastien Bourdeauducq): The build passed.
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travis-ci >
m-labs/misoc#12 (master - 1d60882 : Sebastien Bourdeauducq): The build passed.
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<
GitHub80 >
misoc/master 306235e Sebastien Bourdeauducq: libcompiler_rt: add fixunsdfdi
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travis-ci >
m-labs/misoc#14 (master - 306235e : Sebastien Bourdeauducq): The build passed.
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09:16
<
GitHub63 >
artiq/master c1c3abc Sebastien Bourdeauducq: examples/device_db: add comment about KC705/QC1
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<
whitequark >
sb0: I don't remember any particular reason...
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<
travis-ci >
m-labs/artiq#568 (master - c1c3abc : Sebastien Bourdeauducq): The build was canceled.
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10:06
<
GitHub101 >
artiq/master d06a4d6 Sebastien Bourdeauducq: travis/get-xilinx: use http github clone url
10:07
<
whitequark >
oh, you did the top.bit change already. I was pushing it just now
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10:08
<
whitequark >
sb0: why did you change to http github URL? there's a mandatory redirect to https anyway
10:08
<
whitequark >
this makes no sense
10:08
<
sb0 >
whitequark, even for clone?
10:09
<
sb0 >
github has availability issues right now which are breaking the build, just trying to see if http works any better
10:09
<
whitequark >
you can check it yourself with tcpdump or whatever if you don't believe me
10:09
<
whitequark >
in fact, https is the very reason github doesn't show git:// urls in the UI
10:09
<
whitequark >
because git:// can in principle be MITMed, and https://, well, is slightly harder to
10:10
<
GitHub149 >
artiq/master 56281c1 Sebastien Bourdeauducq: Revert "travis/get-xilinx: use http github clone url"...
10:11
<
whitequark >
in fact,
https://github.com cannot be MITMed in browser once you visited it once, because it pins the public key
10:11
<
whitequark >
unfortunately this won't happen for git clone
10:11
<
sb0 >
ah, now it works
10:12
<
whitequark >
btw, it's almost certain that the availability issues are on the travis side
10:12
<
whitequark >
github is down once a year but travis like biweekly
10:12
<
sb0 >
yes, clone works locally
10:12
<
whitequark >
so next time just restart the build...
10:12
<
sb0 >
i did it twice before committing that ...
10:13
<
whitequark >
there's a reason I used to run my own buildbots
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<
travis-ci >
m-labs/artiq#569 (master - d06a4d6 : Sebastien Bourdeauducq): The build failed.
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<
travis-ci >
m-labs/artiq#570 (master - 56281c1 : Sebastien Bourdeauducq): The build failed.
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10:35
<
kyak >
whitequark: wait a second, are you saying that git@github.com:username/repo.git can be mitmed?
10:35
<
kyak >
i thought it uses ssh for that
10:35
<
kyak >
because, well, i have a ssh key for that
10:36
<
whitequark >
kyak: git@ cannot, git:// can
10:36
<
kyak >
the reason i don't use https repo url on github is because it asks for my username and password. I know git can save the password somehow, but i'm not sure how it works.
10:36
<
whitequark >
yes, https pushes are ugly on *nix
10:36
<
whitequark >
whereas they are much better for windows people
10:37
<
whitequark >
sb0: ERROR:Xst:1817 - Invalid target architecture 'xc7k325t-ffg900-2'.
10:42
<
GitHub64 >
artiq/master d4747a8 Sebastien Bourdeauducq: conda: use vivado for kc705 builds
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<
travis-ci >
m-labs/artiq#571 (master - d4747a8 : Sebastien Bourdeauducq): The build is still failing.
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GitHub110 >
artiq/master ad5a32f Sebastien Bourdeauducq: targets/kc705: remove unneeded argument on qc2
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<
travis-ci >
m-labs/artiq#572 (master - ad5a32f : Sebastien Bourdeauducq): The build was fixed.
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<
GitHub79 >
artiq/master 976e136 Sebastien Bourdeauducq: travis/get-*: fail build earlier on problems
15:44
<
GitHub79 >
artiq/master b13ee2e Sebastien Bourdeauducq: doc: update compilation instructions
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travis-ci >
m-labs/artiq#573 (master - 976e136 : Sebastien Bourdeauducq): The build has errored.
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18:09
<
rohitksingh >
You are welcome! :)
18:21
<
larsc >
isn't there a bot that retweets posts containing credit cards?
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cr1901_modern >
larsc: Not sure. Wouldn't be surprised though.
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23:13
<
cyrozap >
Is it possible to have a write bitslip greater than 4?
23:31
<
cyrozap >
Great news, I got the SDRAM controller working on the Mimas V2!
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