<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vQKja
<openfpga-github>
openfpga/master d466a3f Andrew Zonenberg: Implemented remaining missing macrocell features. Still have to do some global buffers.
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<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vQ6va
<openfpga-github>
openfpga/master db45821 Andrew Zonenberg: Added support for remaining global buffers. Minimal implementation of emulator should be done.
<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vQ6vK
<openfpga-github>
openfpga/master cabe653 Andrew Zonenberg: Fixed typo
<azonenberg>
rqou: so i'm going to have to test more
<azonenberg>
but i think my emulator is done, for some values of done
<azonenberg>
More specifically, full support for arbitrary bitstreams on the XC2C32A, with the caveat that Schmitt trigger, pullup/down, and I/O standard bits are ignored
<azonenberg>
because I don't have the ability to easily reconfigure the FPGA pad ring dynamically
<azonenberg>
And no support for SRAM vs EEPROM programming
<azonenberg>
only EEPROM can be programmed, and the "EEPROM" actually goes straight to the SRAM
<azonenberg>
i'm going to do a bit more testing of this in real hardware then play with JIT for the PLA AND array
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