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<cr1901_modern> It better be the New England kind
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<cyrozap> whitequark: Cert's expired on your IRC logger
<rqou> great, i have a lexer bug that i have no idea how to fix
<rqou> somehow the way i handle strings/extended identifiers is breaking flex's location tracking
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<rqou> blargh, flex yycolumn handling is really poorly documented
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<rqou> sublime text's syntax highlighter for vhdl really likes this :P
<rqou> entity \/*this isn't a comment*/\ is end;
<azonenberg> rqou: lol
<azonenberg> both my normal editor and pastebin's highlighters for nasm
<azonenberg> derp out hard when you use backtick quotes and \' in a string
<azonenberg> like `hello foobar\'s asdf`
<rqou> i also don't know how you're supposed to refer to a design entity with a name like that from e.g. verilog
<rqou> anyways, i decided that instead of doing something useful i was going to write some unit tests :P
<rqou> test coverage is being checked using the very very high-tech technique of "use of highlighters"
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<openfpga-github> [yosys] azonenberg pushed 4 new commits to master: https://git.io/vSkiS
<openfpga-github> yosys/master 0ac72e7 Clifford Wolf: Add generation of logic cells to EDIF back-end runtest.py
<openfpga-github> yosys/master 850f829 Clifford Wolf: Fix EDIF: portRef member 0 is always the MSB bit
<openfpga-github> yosys/master 1390e9a Clifford Wolf: Add simple EDIF test case generator and checker
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<rqou> oh great, i found another parser bug
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<whitequark> cyrozap: fixed
<rqou> aaargh i hate subtype_indication
<rqou> currently playing bug whack-a-mole
<rqou> hrm, i have fixed my bug but I don't understand why it has become fixed
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<rqou> someone should really help me test my subtype_indication parsing
<rqou> whitequark: can you share details about your experience with a "custom in-house programming language?" (from twitter)
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<whitequark> rqou: well, which one of the two? I wrote both :p
<rqou> why not both? :P
<whitequark> rqou: the first one was a not-invented-here version of rust and therefore killed off in favor of using rust
<whitequark> (well, i didn't know about rust when i was writing it and also rust was rather unlike modern rust back then anyway)
<whitequark> the second one is alive and well and is used in ARTIQ
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<rqou> hrm, interesting
<rqou> is "the second one" migen?
<rqou> or do you guys have yet another DSL?
<rqou> btw my example of "company with a custom in-house programming language" was national instruments
<whitequark> rqou: migen is not a language
<whitequark> and yes, we have "ARTIQ Python", which is a statically typed mostly subset of Python
<rqou> i mean, you _could_ consider sufficiently "weird" (different from the host) DSLs as a separate language
<whitequark> rqou: the point of migen is that it's not a language
<nats`> it's a subset of python :D
<nats`> like CLaSH is a subset of haskell
<rqou> wait, so migen is _deliberately_ not a deep embedding (unlike myhdl)?
<whitequark> nats`: um, no, you don't understand how migen works
<whitequark> rqou: see the second paragraph in https://m-labs.hk/migen/manual/fhdl.html
<rqou> hrm, i thought myhdl also gave you access to manipulate asts?
<rqou> maybe that's internal/not officially supported
<whitequark> it may not have been there when migen was conceived, too
<rqou> quite possibly
<rqou> it's pretty funny how i'm working on an hdl tool but i don't even know any hdls that well :P
<rqou> welcome to $FANCY_SCHOOL, where they teach you all the theory and the details are all "you can figure it out on your own"
<rqou> it sucks how we still don't have any good common HDL IRs
<rqou> no, "some ad-hoc but mostly-agreed-upon subset of verilog" isn't an IR
<nats`> <whitequark> nats`: um, no, you don't understand how migen works <= for me it's a lib like system C
<nats`> and it generates verilog from a subset of python using that lib
<whitequark> nats`: it's not
<nats`> ah ?
<whitequark> it's *specifically* not
<whitequark> it's silly to use deep embedding for anything that isn't lisp because the ast of the host language is a poor choice for an abstract representation of the embedded language, except in very rare cases
<rqou> what about scala/chisel?
* rqou hasn't used that either despite it being a $FANCY_SCHOOL project
<nats`> so what is migen
<nats`> it is described as a python module
<whitequark> rqou: the only times i ever heard about scala is when it involved some indescribable type system horrors
<whitequark> and i'm strongly of the opinion of "when it hurts, maybe you should stop doing that"
<whitequark> i have no other opinion on that
<rqou> you don't want SKI calculus implemented in your type system? :P
<rqou> hey, rust also has an undecidable type system i heard
<whitequark> who cares about decidability?
<whitequark> in scala it's a libs issue
<rqou> it'd be nice if your compiler could always definitively accept/reject your program
<whitequark> nats`: you describe a circuit using python code, somewhat like a flowgraph
<whitequark> rqou: rust has a recursion limit
<whitequark> so it will definitely reject your program past some point
<rqou> that barely counts i guess
<rqou> in that case so does scala's compiler and c++ compilers
<whitequark> yes
<whitequark> i have no problems with undecidability. undecidability is useful. decidability is not obviously useful in general
<rqou> in my very very limited playing with scala i didn't encounter any weird type system issues
<rqou> but then i wasn't really making use of any collections
<rqou> in general i find JVM languages a pain to deal with
<whitequark> jvm is pretty sweet
<rqou> even getting a nontrivial project to compile without blindly throwing everything in eclipse and hitting build is hard
<whitequark> it has a usable profiler and debugger, it's pretty fast
<whitequark> python has none of those
<whitequark> hope you like sticking print()s everywhere
<rqou> when i needed "debugging" and speed i would use ipython notebook + numpy
<rqou> i've never really needed a profiler
<rqou> in the (probably insufficiently complicated) projects i've worked on "thinking about it" was a far better optimization technique than "use a profiler"
<rqou> actually that's not completely true
<whitequark> "i've never really needed a profiler" um
<rqou> i've done "profiling" with the "GPIO_PIN = 1; do_stuff(); GPIO_PIN = 0;" technique on a microcontroller
<whitequark> i mean sure if you've never wrote real code that would influence your choice of languages
<whitequark> even if you exclusively work with batch jobs, at some point they get too slow.
<rqou> i mean, i did mention that i've used numpy when i had to crunch a lot of data
<rqou> usually if the program was still too slow the only workable optimization technique was to get out the whiteboard/scratch paper and mathematically simplify what was being calculated
<rqou> (in case you can't tell, this was also homework :P )
<rqou> i really haven't written software that is a "real product"
<rqou> i've written a lot of code for my own learning/experimenting/hacking and for homework
<rqou> but never really anything that other people had to use
<whitequark> a profiler is one of those things that you never know you need until you do, and then it's indispensable
<whitequark> i'm about to write a profiler for artiq...
<whitequark> (the firmware)
<rqou> does "GPIO_PIN = 1; do_stuff(); GPIO_PIN = 0;" not count?
<whitequark> (though it may be useful for kernels too)
<whitequark> not really, you want a sampling callstack profiler usually
<rqou> artiq uses a soft-cpu, right?
<whitequark> sure
<rqou> can't you easily implement a sampling profiler that just dumps PC into a block ram?
<whitequark> no? that doesn't give you the callstack
<rqou> ah you actually want the full callstack
<whitequark> it's also completely unnecessary, a timer interrupt works just as well and is less effort
<rqou> unless you somehow have heisenbugs that are affected by the presence of the timer interrupt? :P
<whitequark> I can implement an interrupt-based sampling profiler in probably less time that xilinx tooling runs once
<rqou> lool
<whitequark> 22 minutes
<rqou> has nobody implemented an arm ETM clone for an open softcore?
<whitequark> dunno
<whitequark> mor1kx implements a PMU
<whitequark> (which is broken by design because lol)
<rqou> why?
<whitequark> unless you use it in a very specific way, it randomly loses events
<whitequark> this specific way is in no way (no pun intended) alluded to in the architecture documentation
<rqou> was this introduced in the mor1kx rewrite or did it originate from the (afaik crappy) original or1200 design?
<whitequark> i don't know if PMU was ever implemented in or1200
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<rqou> is it that writing to pccr will be ignored if it coincides with an event occurring?
<rqou> there's also the classic "events get missed when pcmr is changed"
<rqou> i don't see anything that "randomly" loses events in the simple "it just counts up" case
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<rqou> wait
<rqou> i think i'm reading it wrong
<rqou> you can only safely have one bit set in pcmr at a time
<rqou> otherwise simultaneously occurring events will only have one of them counted
<rqou> whitequark: is this is?
<whitequark> yes
<rqou> hooray for nonblocking assignments? :P
<rqou> is the broken behavior mandated or can you make a fork/different implementation that changes it?
<whitequark> it's not, it's a bug in mor1kx
<rqou> so send a pr to fix it?
<whitequark> so write it?
<rqou> TooManyProjectsException :P
<whitequark> BrainTimesOutWaitingForXstException
<rqou> just test in icarus and not in hardware? :P
<rqou> um, i'm assuming mor1kx doesn't fit in the hx8k?
<whitequark> rqou: it does, but you have to cut it down rather severely
<rqou> i'm assuming no cache, no mmu, no fpu?
<whitequark> correct
<rqou> wtf the vhdl package_pathname rule is different in section 8 vs annex c
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<cr1901_modern> I thought that mor1k issue was already reported?
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<nats`> <whitequark> nats`: you describe a circuit using python code, somewhat like a flowgraph <= like systemC ?
<nats`> but using a lib to generate the verilog behind
<nats`> I'm not sure to see a big difference here
<whitequark> nats`: sorry, I guess I am not being very clear
<whitequark> migen does not map python ASTs directly to logic
<whitequark> it doesn't really work with python ASTs at all
<nats`> yep I agree with that
<nats`> that's why I said it's a library
<whitequark> what it does is it lets you construct data, that is then mapped to verilog
<nats`> you call it
<nats`> yep sure :)
<whitequark> as far as I know, with systemC, you have C code that's converted to logic
<whitequark> is that not true?
<nats`> I can't remember well
<nats`> SystemC is a lib IIRC
<nats`> need to check that
<whitequark> nats`: hm, actually I read up on systemc and it *is* like migen
<whitequark> sorry about that, I misunderstood something somewhere
<whitequark> was pretty sure systemc uses a deep embedding
<whitequark> but I must have thinking of one of the logic extraction tools
<nats`> no problem I wasn't 100% sure either :)
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