<rqou> afl seems to quite like left paren :P
<rqou> probably opens up the most codepaths
m_w has quit [Quit: Leaving]
ZipCPU|Laptop has joined ##openfpga
m_w has joined ##openfpga
digshadow has quit [Quit: Leaving.]
pie__ has quit [Ping timeout: 246 seconds]
<lain> afl reinvents lisp inside vhdl
<cyrozap> "But what _is_ water? It's a difficult question, because water is impossible to describe. One might ask the same about _whitelogger. Who _is_ _whitelogger? We just don't know."
cr1901_modern has joined ##openfpga
<rqou> hrm, parser is throwing "memory exhausted" at "a <= a(a(a(a(a(a),a(a <= a, a(a), a < 9)))));"
<rqou> egg|egg: ideas? :P
<rqou> hrm, i can make yymaxdepth bigger
<rqou> but why am i already exceeding it?
<lain> infinite recursion?
<rqou> i mean, the grammar is inherently infinitely recursive
<rqou> i think glr just uses a shitton more stack space
<rqou> wow some of these take a really long time to parse and then error
<rqou> which is why afl was timing out on them
<rqou> should "is ridiculously slow" be considered a bug?
<rqou> so apparently bison does have a known issue in glr mode where certain error recovery scenarios can hang forever
<rqou> hrm, 10 seconds to report a parse error seems pretty bad
<lain> lul
<rqou> i have this line here that seems to hang the parser forever: a (a range a((a(a+a/a=a(2a/a.a(a=a(2a/a=a/a(a((a((a+a=a,2a/a=a(2a/a.a(a=a(2a/a=a(2a/a(a+a=a,2a/a=a(a
<lain> I think fuzzing parsers for something like vhdl is silly
<rqou> i'm trying to find places where my ebnf is ambiguous
<lain> ah
<rqou> because i'm running in GLR mode, not normal LALR mode
<rqou> afaik GLR basically = LALR+NFA trick
<rqou> this might not actually be an infinite loop here
<rqou> it might be the mis-feature of bision GLR taking exponential time
<rqou> oh i found a crash!
<rqou> not a parse ambiguity though?
<rqou> looks like a bog-standard coding issue
<rqou> aaanyways, lain you were saying that fuzzers are useless? :P
<lain> I just don't think fuzzing is an effective way to find bugs in a compiler or related parser
<lain> fuzzing is great for finding obscure bugs in something that accepts input from, say, the internet :P
<rqou> yeah, this was your bog-standard "missing null check" in the "debug dump AST" function
<rqou> i really need a fuzzer specifically for parsers
<rqou> btw sqlite got fuzzed and parser bugs were found
<rqou> honestly somebody here should help contribute and write a VHDLHammer similar to clifford's vloghammer
<rqou> (once i get more stuff working of course)
<rqou> vloghamemr will probably have way way more corner cases
<rqou> *vhdlhammer
<rqou> i haven't even _started_ on semantic analysis or elaboration
ZipCPU has quit [Ping timeout: 264 seconds]
digshadow has joined ##openfpga
ZipCPU has joined ##openfpga
GreeningGalaxy has quit [Ping timeout: 260 seconds]
digshadow has quit [Quit: Leaving.]
digshadow has joined ##openfpga
<rqou> yeah i _definitely_ have some kind of exponential time algorithm problem
<rqou> even afl starts getting slowed by it
<rqou> it only really happens with certain input patterns
GreeningGalaxy has joined ##openfpga
amclain has quit [Quit: Leaving]
DocScrutinizer05 has quit [Disconnected by services]
DocScrutinizer05 has joined ##openfpga
GreeningGalaxy has quit [Quit: zzzzzzz]
Bike has quit [Ping timeout: 258 seconds]
Bike has joined ##openfpga
Hootch has joined ##openfpga
digshadow has quit [Quit: Leaving.]
m_w has quit [Quit: leaving]
digshadow has joined ##openfpga
digshadow1 has joined ##openfpga
digshadow has quit [Read error: Connection reset by peer]
digshadow has joined ##openfpga
digshadow1 has quit [Read error: Connection reset by peer]
_whitelogger has joined ##openfpga
_whitelogger has joined ##openfpga
cyrozap has quit [Ping timeout: 264 seconds]
<rqou> why are video capture programs/hardware all seem to be unbelievably crappy?
cyrozap has joined ##openfpga
<rqou> (context: watching @scanlime's stream)
digshadow has quit [Quit: Leaving.]
azonenberg_work has quit [Ping timeout: 268 seconds]
digshadow has joined ##openfpga
massi has joined ##openfpga
<egg|egg> rqou: does the cat count as video capture hardware?
<rqou> lol
<rqou> i don't think so? :P
<rqou> egg|egg: btw parser testing: http://i.imgur.com/boGsGWk.png (WARNING HUGE)
<egg|egg> O_o
<rqou> anyways, this isn't the most optimal tool for testing the parser, but it requires minimal setup
<egg|egg> "american fuzzy lop" sounds odd somehow
discrttm has quit [Read error: Connection reset by peer]
discrttm has joined ##openfpga
<rqou> so i just went down to "southside" (the (in)famous Telegraph Avenue area) for the first time in a while and I forgot how great the "aroma" was :P
clifford has quit [Ping timeout: 260 seconds]
Bike has quit [Quit: slerp]
<jn__> egg|egg: it's a bunny
<jn__> (and i first thought it's called "american fuzzy loop", because that seems to make sense, but no, it isn't)
promach has joined ##openfpga
pie_ has joined ##openfpga
pie_ has quit [Ping timeout: 246 seconds]
clifford has joined ##openfpga
clifford has quit [Remote host closed the connection]
pie_ has joined ##openfpga
ZipCPU|Laptop has quit [Ping timeout: 240 seconds]
promach has quit [Ping timeout: 256 seconds]
promach has joined ##openfpga
ZipCPU|Laptop has joined ##openfpga
ZipCPU|Laptop has quit [Quit: Leaving]
Bike has joined ##openfpga
pie_ has quit [Ping timeout: 256 seconds]
amclain has joined ##openfpga
azonenberg_work has joined ##openfpga
massi has quit [Remote host closed the connection]
azonenberg_work has quit [Ping timeout: 246 seconds]
promach has quit [Quit: Leaving]
digshadow has quit [Ping timeout: 240 seconds]
pie_ has joined ##openfpga
azonenberg_work has joined ##openfpga
pie_ has quit [Ping timeout: 240 seconds]
digshadow has joined ##openfpga
m_w has joined ##openfpga
pie__ has joined ##openfpga
pie_ has joined ##openfpga
asy has joined ##openfpga
Zarutian has joined ##openfpga
m_w has quit [Quit: Leaving]
<Zarutian> h'lo folks.
<Zarutian> what does RE stand for in topic?
<jn__> reverse engineering
<Zarutian> should have known ;-Þ
<Zarutian> I had some moons ago looked into reconfigurable computing. Found it neat concept but I was irritated because Xlinx (the main introducer of the concept) bitstream format being no-where openly specified and hence such parts could not be synthesized dynamically (even just changing a constant) by code running in a small softcore or on coprocessor on the same chip.
<Zarutian> here and now I ask, which chip or chiplines have been reverse engineered that supports partial reconfigurability?
<rqou> xilinx? basically none
<rqou> feel free to help
<Zarutian> meant in general
<rqou> there was some initial work done for Spartan 6 and 7-Series bitstream RE
<rqou> not complete enough to do anything
<rqou> lattice ice40 is more-or-less completely REd but isn't dynamically reconfigurable
<rqou> xilinx coolrunner 2 cplds are about 90% understood on the bitstream side but place and route hasn't gotten anywhere
<Zarutian> yebb saw the CCC talk (even asked via irc exactly about if it was dynamically reconfigurable ;-)
<rqou> if you want nightly precompiled binaries for the ice40 tools (and you trust binaries built by some random dude on the internet): https://rqou.com/jenkins/job/open-fpga-tools/
<Zarutian> the place and route step is done by the toolchain on the developers machine isnt it? (Hasnt done much fpga or clpd programming, just mcu)
<rqou> yes
<rqou> azonenberg is currently working on code that does place and route for silego's greenpak pmic chips
<Zarutian> which is pretty much constraint fitting given a spefic chip
<rqou> this should be adoptable to other cplds
<rqou> but I haven't made much progress getting that to work
<pointfree> o/ Zarutian
<rqou> I've currently shelved cpld work and am currently working on a vhdl parser
* Zarutian rather dislikes vhdl and verilog (would be better off with something like BLIF)
<rqou> yosys accepts blif afaik
<rqou> I don't know too much about blif
<pointfree> Zarutian: Vincent Jordan does free/open partial dynamic live reconfiguration for Spartan 6 LX9. https://vjordan.info/flr/ http://vjordan.info/log/fpga/category/fpga.html
<rqou> wait, s6 got finished/un-bitrotted?
<rqou> why isn't there a working PAR?
<pointfree> Vincent Jordan isn't using Wolfgang-Spraul/fpgatools
<pointfree> ...but he's doing partial live reconfig over jtag
<rqou> but that means he has the bitstream REd, including PIPs?
<cr1901_modern> I've seen wolfspraul speak exactly once since this room was created lol
<pointfree> rqou: I think Vincent Jordan did the routing as well. His blog https://vjordan.info/flr/ is an interesting read that got less attention than it deserved.
<rqou> hrm, so anyone want to use that info to port vpr to s6?
<rqou> I would do it except I'm waaay overloaded with projects already
<pointfree> Zarutian: The PSoC 5LP supports dynamic reconfiguration.
<rqou> right, I keep forgetting about psoc :P
<rqou> I keep having the impression that it's not a "real" fpga
<rqou> but then neither is greenpak
<pointfree> rqou: Well, it should even be possible to synthesize to (register) machine code not just to fpga/cpld. I think it has been done before.
<pointfree> machine instructions are just hard-ips
m_w has joined ##openfpga
Hootch has quit [Quit: Leaving]
digshadow1 has joined ##openfpga
digshadow has quit [Read error: Connection reset by peer]
pie___ has joined ##openfpga
pie____ has joined ##openfpga
pie__ has quit [Ping timeout: 258 seconds]
pie_ has quit [Ping timeout: 240 seconds]
<pointfree> I posted vjp's Spartan 6 RE and fpgalivereprog all over reddit and few people cared. I think he indicated to me that this is why he kinda stopped working on it.
<pie____> fpga liver prog?
<pointfree> re-prog
<pie____> i know i was trying to make a crappy joke :P
<pointfree> :)
<pie____> well....you probably shouldnt do RE if you want the masses to be interested...
<pie____> :(+
<pie____> * :(
<pie____> much less hardware
<pie____> not that id know
<rqou> yeah i didn't ever hear about it
<rqou> i guess i'm not the only person here bad at "SEO"
azonenberg_work has quit [Ping timeout: 264 seconds]
<pointfree> His blog is hosted on a raspberrypi with and used a self-signed cert.
<pointfree> s/with//
<rqou> hrm, i see a LE cert
<rqou> but _that's_ why it's so slow :P
<pointfree> He got rid of the self-signed cert. It scared off some people.
<rqou> yeah i love how LE is destroying the CA protection racket
<rqou> they finally stopped being "problematic" and started allowing IDNs too
<rqou> now the only thing i'm unhappy with about them is their lack of transparency about "forced" (by e.g. Microsoft) revocations
digshadow has joined ##openfpga
digshadow1 has quit [Quit: Leaving.]
digshadow has quit [Quit: Leaving.]
digshadow has joined ##openfpga
<rqou> hrm, according to the twitter tencent demonstrated a vmware guest-to-host escape
<rqou> still waiting patiently for a "browser to both EL3 and hexagon baseband simultaneously" exploit :P
X-Scale has quit [Ping timeout: 240 seconds]
X-Scale has joined ##openfpga
X-Scale has quit [Ping timeout: 258 seconds]
X-Scale has joined ##openfpga