<mithro>
ZipCPU: it gets optimised down to 6 LUTs if I understand correctly...
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<daveshah>
mithro: putting `(* keep *)` on all the submodules should work
<daveshah>
Otherwise, I think there's a way of running abc on the submodules rather than the flattened design, by running hierarchy after abc
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<mithro>
daveshah: Well, ideally I would like a design which /can't/ be optimized away
<mithro>
daveshah: I feel like maybe you could use a SAT solver to fill in the LUT init pattern to make sure?
<ZipCPU>
That was what the reddit/yosys article discussed, "Keep duplicate FF through Opt_merge". Clifford demonstrated in the response that you could keep ABC from optimizing sections of your design via the (* keep_hierarchy *) attribute.
<mithro>
ZipCPU: Yeah - knew about the keep stuff - but I was more looking for something that can't be optimized away...
<daveshah>
That design will always be optimised unless the optimiser is broken
<daveshah>
No SAT solver will help with that
<daveshah>
Either you need more inputs or a keep command
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<mithro>
daveshah: Out of interest how would you "prove" that?
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<daveshah>
Not sure TBH
<daveshah>
Actually, I was thinking about an arch with muxes. Too much ECP5 stuff
<daveshah>
Maybe there is a pattern that works
<mithro>
daveshah: Well, I guess you have "existence proof" -- IE ABC was able to optimize it so, therefore... :-P
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<daveshah>
I think this is a proof that a 6-input combinational network will produce no more than 6 LUT4s after optimisation: A 6-LUT can always be built from 4 4-LUTs and a MUX4. Proof by Yosys that a MUX4 can be built using only 2 LUT4s. Hence 6 LUT4s in total
<daveshah>
Feel free to point out a flaw in this
<cr1901_modern>
4 4-LUTs (I can visualize a MUX4 from 2 4-LUTs just fine)?
<cr1901_modern>
Basically, I don't see how you get 6 bits of arbitrary functions from 4-LUTs and a MUX
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<cr1901_modern>
Wait nevermind. I can visualize a 5-LUT from 2 4-LUTs and a 2-MUX, so 6-LUT is just an extension of that (too lazy to actually do it in my head tho :P)
<sorear>
what does the MUX4 from LUT4 look like?
<sorear>
i couldn't figure out how to do it with less than 3 myself
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<photon>
any recommendation for a sequence of abc command to minimize the area?
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<ZipCPU>
Doesn't the "opt" yosys command do that?
<photon>
well, opt does not do a great job
<ZipCPU>
If there's another means of doing so, I'd like to find it. I've got some code I'd like optimized better .. ;)
<photon>
for a test design design compiler gave 160 gates and yosys/abc gave 1000 gates!
<awygle>
are you also running "abc"?
<photon>
I played abit with abc commands to reduce the number to 600 gates
<photon>
but, it is still far away from 160 gates
<photon>
reported by DC
<ZipCPU>
"gates" or "LUT"s?
<photon>
I am mapping the design to ASIC standrd cell library
<ZipCPU>
Does your design have RAM elements within it?
<photon>
if they do good job for ASIC they should for FPGA
<photon>
it is a pure combinational design given as a set of boolean equations
<cr1901_modern>
sorear: Gonna have to take a rain check on that one. My mental picture was wrong. But I imagine it can be done
<sorear>
cr1901_modern: i'm asking daveshah not (necessarily) you
<cr1901_modern>
sorear: Oh sorry, I made it all about me :P
<sorear>
you can answer it if you want, but I don't expect you to know details of daveshah's 2-LUT MUX4