clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
<mithro> So, I don't understand when I should use "prep" and when I should use "synth" in yosys?
<ZipCPU> mithro: prep for formal
<ZipCPU> let me check a bit deeper tho
<mithro> Should the following describe a 4 input, 1 output lut?
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<ZipCPU> Sure looks like it!
<ZipCPU> You might wish to notice, though, that prep doesn't read in any cell libraries
<ZipCPU> As a result, if you run prep on that you probably won't get a 4-input LUT
<mithro> So, yosys seems to outputting the following blif file
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<mithro> ZipCPU: I'm using synth at the moment...
<ZipCPU> What architecture are you trying to target?
<mithro> yosys -p "synth; abc -lut 4 opt_clean; write_blif -attr -cname -conn -impltf -param build/testarch/2x4/vlut.eblif" vlut.v
<ZipCPU> What architecture are you trying to target?
<mithro> A test architecture that doesn't really exist....
<mithro> Any idea why the missing semicolon between abc and opt_clean didn't cause yosys to error?
<ZipCPU> Because opt_clean was taken to be an argument to abc
<mithro> ZipCPU: yosys doesn't check args passed to abc and/or abc doesn't error on the opt_clean extra argument?
<ZipCPU> that follows from your description, does it not? I haven't checked the yosys code, and you've got the log file.
<mithro> Yeah - it seems so
<mithro> Just testing more now
<ZipCPU> I was at one time surprised when clifford explained to me what opt -share_all did. It called the "opt" process and applied it to "-share_all" portion of my design
<ZipCPU> I had been using it in all my designs up to that point.
<ZipCPU> Oops
<mithro> ZipCPU: Now I have the semicolon things seem to work... I'm getting a single 4 input lut...
<ZipCPU> ;)
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<mithro> Hrm, yosys isn't generating the .attr and .param values I'd expect...
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<awygle> mithro: there's a flag to generate .attr and .param compatible with arachne
<awygle> Is that what you're expecting?
<mithro> awygle: Yeah -- using the http://www.clifford.at/yosys/cmd_write_blif.html
<tpb> Title: Yosys Open SYnthesis Suite :: Command Reference :: write_blif (at www.clifford.at)
<mithro> write_blif -attr -cname -conn -impltf -param out.eblif
<awygle> Hmm OK you're already using attr and param
<mithro> awygle: I'm getting .conn - so some part of it is working...
<mithro> awygle: Ahh - it seems to only set .attr on .subckt -- not on .names and .latches .....
<awygle> Ahh
<tpb> Title: When should yosys be generating extended eblif attributes? · Issue #533 · YosysHQ/yosys · GitHub (at github.com)
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<tpb> Title: TinyFPGA BX - TinyFPGA B2 and BX Projects! | Crowd Supply (at www.crowdsupply.com)
<tpb> Title: PicoEVB | Crowd Supply (at www.crowdsupply.com)
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<tito_> hi
<janrinze> hi
<tito_> help to use Diamond FPGA, I posse ice40 1k stick , i'm nabbo I can not create projects, and I have to insert fail to do vga ....... link for me
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<tito_> help to use Diamond FPGA, I posse ice40 1k stick , i'm nabbo I can not create projects, and I have to insert fail to do vga ....... link for me
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<mazzoo> hello
<mazzoo> I'm playing with picosoc and some firmware...
<mazzoo> this works nicely: https://pastebin.com/0v8fWRu8
<tpb> Title: [C] // -------------------------------------------------------- #define LEN_HEART - Pastebin.com (at pastebin.com)
<mazzoo> (it's a simple POV heart) but I can't declare the sign_heart outside of the function
<mazzoo> even as static it won't work
<mazzoo> what am I missing?
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<tito_> hi help to use Diamond FPGA, I posse ice40 1k stick , i'm nabbo I can not create projects, and I have to insert fail to do vga ....... link for me
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<ZipCPU> tito_: You asked a week ago. You claimed to be a newbie, and were trying to place projects (not even built ones) on boards for which they weren't designed.
<ZipCPU> Further, you were unwilling to learn how to do a design in order to make those projects fit.
<ZipCPU> I'm not sure how I could help you at this point.
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<tito_> I'm not able to make drawings, I'm not even able to open projects, I can not use the programs for fpga, I have an usb ice40 and I have to turn it into vga, I need links, to upload files and I do not understand
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<ZipCPU> You may have to explain some more: why can't you make any drawings? and how do you intend to turn an ice-stick into an VGA, if it doesn't have a VGA connector on it?
<ZipCPU> Opening projects I can teach, but not if you have no willingness to learn.
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<shapr> yay chicago adventures!
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<sorear> Oh?
<tito_> I understand only that a usbstick can be programmed and transformed into vga. I do not know any other problems like pins or connectors. I bought an economic ice40 having files, to try ..... but having the files I was hoping not to have problems, to open the program and copy to fpga, now I think it is not possible to transfer fpga files in a simple way as an open / save.
<daveshah> tito_: What VGA files were you expecting to try?
<ZipCPU> tito_: You might've had more success if you purchased the same FPGA that was used in the VGA demo project you were looking at: a Spartan 6 (I'd have to look up which one). Most Spartan 6's have a lot more resources than an iCE40.
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<ZipCPU> It may not even be possible to place a Spartan 6 design onto an iCE40 -- especially not a 1k iCE40, but then again ... there are designs that will fit.
<mazzoo> BTW: does a picorv32 together with a (e.g.) SimpleVOut fit on an 8k iCE40?
<knielsen> probably; I remember putting picorv32 on an 8k along with some simple support logic, taking ~ 50% of luts
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<sorear> shapr: Chicago?
<shapr> sorear: yup, are you in chicago?
<shapr> sorear: if yes, want to hang out and chat this evening?
<sorear> shapr: unfortunately no
<sorear> shapr: i'm in Boston rn; forget if I ever told this channel
<sorear> [was asking what the chicago adventures were]
<tito_> I also found https://github.com/lattice/quda but the problem is always that they are files ........ and I can not find guides to transfer and I do not understand. I can not even talk to ice ........
<tpb> Title: GitHub - lattice/quda: QUDA is a library for performing calculations in lattice QCD on GPUs. (at github.com)
<shapr> sorear: oh, I'm giving a Haskell intro at the south side hackerspace chicago
<sorear> [incidentally if anyone here IS in the greater MIT area…]
<shapr> sorear: I would have looked you up this past November if I'd known that
<sorear> shapr: i've been here three weeks, before that I was in San Diego
<shapr> oh
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<tito_> hi
<tito_> I would have 1 question
<mithro> Clifford was interested in posits IIRC?
<mithro> Does anyone know why this set of -luts arguments was chosen for Xilinx Synth ? --> abc -luts 2:2,3,6:5,10,20
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