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<
ZipCPU>
keesj: You've been trying to build an FPGA command and control link via a serial port, right?
<
ZipCPU>
Having any success?
<
keesj>
Well. I decided I was going to use wishbone today hence will first try that approach
<
keesj>
I think the solution will be nicer if i write the glue logic in a soft cpu (serial->cpu<-can_controller)
<
ZipCPU>
Got enough wishbone information to get yourself going?
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<
keesj>
Well. I did a similar project (on SPI triggers) before but this is from scratch :P
<
ZipCPU>
You were posting in the VHDL channel. What brings you to yosys, since yosys is primarily a verilog tool?
<
keesj>
But this is my first time on this channel (I have been active on ##vhdl)
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<
ZipCPU>
I've got most of my TinyFPGA design done ... just still need to prove that the flash controller I just built works as designed.
<
keesj>
are you working on that?
<
ZipCPU>
I'm not employed working for the TinyFPGA team.
<
keesj>
Anyway at FOSDEM I also saw some nice projects around yosys hence .. I will need to investigate this later. First .. make my project work
<
ZipCPU>
Ok, sure, welcome to the channel!
<
ZipCPU>
<shameless plug> Feel free to browse the ZipCPU blog as well, at zipcpu.com </shameless plug> :)
<
keesj>
:p (currently using the papilio pro and the zpuino soft core)
<
ZipCPU>
Sure. A tiny zpuino core makes a lot of sense for an iCE40 design.
<
keesj>
I have read your website before nice to meet on IRC
<
ZipCPU>
That's me!
<
ZipCPU>
Been trying to formally verify the ZipCPU today, and so far I've been
*quite* successful!
<
tpb>
Title: GitHub - cliffordwolf/picorv32: PicoRV32 - A Size-Optimized RISC-V CPU (at github.com)
<
ZipCPU>
Yes, it is quite interesting. I've looked over it myself, although I've never tried it.
<
keesj>
I only listened to it on the amp hour podcast (374)
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