clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<daddesio> Does anyone know the proper timing to send an infinite stream of "AAAAA..." over uart to a pc? I'm sending "010000010101000001010100000101..." with a 9600Hz clock (9600 bits per second) -- I confirmed this in both gtkwave and the oscilloscope at my workplace -- but "sudo screen /dev/ttyUSB0 9600" is completely blank.
<mazzoo> start and stop bits?
<daddesio> I can insert more 1s in between characters, like "0100000101 1111111111 0100000101 1111111111", but it doesn't make a difference
<daddesio> I'll see if I can output the same signal from my usb uart and compare with my fpga output.
<mazzoo> perl -e "print 'A' x 9001" > /dev/ttyUSB0
<mazzoo> after setting the baud with stty
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<daddesio> Figured it out! I was passing the 12MHz clock to my module by mistake instead of the 9600Hz clock that I calculated.
<daddesio> so "I confirmed this on my oscilloscope" was wrong.
<daddesio> I only confirmed the 9600Hz clock and 9600Hz square wave were right, not my new 9600 baud "A" generator.
<daddesio> Aha, the issue is in my pcf file: set_io clk 21
<mazzoo> jfyi: FTDI USB UARTs work up to 3MHz
<mazzoo> real world cable limits make 2MHz possible
<daddesio> I renamed the variable recently, so it should say set_io clk_12mhz 21 now
<awygle> or you can run Fast Serial at 50 MHz :p
<mazzoo> awygle: what is Fast Serial?
<awygle> it's basically a UART+Clock
<awygle> perhaps a USRT
<awygle> or if you prefer, like SPI without the slave output
<awygle> although that analogy's not as good
<mazzoo> nice! never noticed that part of the datasheet...
<awygle> credit goes to ZipCPU for pointing it out
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<ZipCPU> awygle: Ever thought of trying it out?
<awygle> ZipCPU: i think of lots of things :)
<awygle> i haven't yet had occasion to though, no
<ZipCPU> Yeah, me neither.
<ZipCPU> I've wanted to though.
<ZipCPU> It was a Pennsylvania engr who pointed the capability out to me.
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