<keesj>
ZipCPU: in your blog post http://zipcpu.com/zipcpu/2017/05/29/simple-wishbone.html you talk about the o_wb_ack saying "there must be one and only one clock cycle with o_wb_ack high" but later you say "you might just assign the o_wb_ack signal instead of waiting for the positive edge of the clock" is this a contradiction?
<tpb>
Title: Building a simple wishbone slave (at zipcpu.com)
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<ZipCPU>
Morning' keesj!
<ZipCPU>
I guess I don't understand the contradiction you are trying to point me to yet.
<ZipCPU>
Ahh, okay, I get it ... the issue is what you would assign the o_wb_ack signal to. It's not assigned to high, but rather to (i_wb_stb)&&(!o_wb_stall).
<ZipCPU>
On the peripherals I'm discussing, o_wb_stall would be zero, hence o_wb_ack would become equivalent to i_wb_stb
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<ZipCPU>
keesj: I just adjusted the article. Hopefully that will make the issue clearer. Please let me know if you still have questions, or if you think the (updated) version isn't clear enough (yet).
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