<ZipCPU>
Yeah, so ... you can read the post if you like, or I can tell you the story ... :)
<ZipCPU>
The story goes back to a dark man, with a dark purpose, waiting on a dark night ... Oops, sorry, that's Aladdin ... let me try again ...
<ZipCPU>
No, seriously, I was programming my very first FPGA. The hardware engineer had delivered me a circuit board. The Linux engineer had placed a Linux distro on the ARM chip on that board. The FPGA was connected via an auxiliary bus to the ARM chip.
<ZipCPU>
The hardware engineer who had "proved" that the board worked, gave it to me empty with only one configuration on it--one that allowed the reading from or writing to bus addresses.
<ZipCPU>
Hence, from the Linux program I could read from a memory-mapped address within the FPGA.
<ZipCPU>
My first program mapped a 3-bit input from an offset A/D into a 4'bit value that would properly handle the task. I tested it via writing the value to the bus, and reading the result back off.
<ZipCPU>
I managed to use that same basic interface to build a GPS front-end processing system, and again to build a custom radio system.
<ZipCPU>
The custom radio was fascinating, since I would write to a "clock register" that would step the entire design. I could then come back and read information back off at my convenience, one word per clock.
<ZipCPU>
I'd write the "input" from the antenna (i.e. simulation) into one register, and then watch as it cascaded through the processing chain.
<ZipCPU>
On the whole, I found the technique quite useful at the time.
<ZipCPU>
In hind sight, I might've moved through the project faster if I had used simuation--since it would take ISE (Spartan 3) about 15 minutes to build each test design, and I can often simulate something in less than a minute or two.
<ZipCPU>
When I had to stop stepping the design, it was as easy as setting that step register field to a 1'b1, and all the debugging code would be optimized out of the design.
<ZipCPU>
When I switched to full speed, I had two problems. The first I solved with the predecessor of the wishbone scope, creating something like a chipscope capability. The other was the fact that ... my simulated radio matched the receiver clock perfectly. Oops. Reality was a touch more difficult.
<ZipCPU>
The funny part was the response of the veteran FPGA designers watching me with my first design. In general, they just shook their heads in dismay. When I delivered, they then scratched their heads somewhat. Either way, the approach was an anomaly.
<ZipCPU>
philtor: That's the basic story.
jkiv has quit [Ping timeout: 246 seconds]
pie_ has quit [Ping timeout: 256 seconds]
Marex has quit [Remote host closed the connection]
Marex has joined #yosys
cemerick_ has joined #yosys
cemerick has quit [Ping timeout: 240 seconds]
milkii has left #yosys ["Leaving"]
kuldeep has quit [Quit: Its never too late!]
sandeepkr has quit [Quit: ZNC 1.6.5 - http://znc.in]
kuldeep has joined #yosys
digshadow has quit [Ping timeout: 276 seconds]
xrexeon has quit [Ping timeout: 255 seconds]
cemerick_ has quit [Ping timeout: 265 seconds]
AlexDaniel has quit [Ping timeout: 240 seconds]
digshadow has joined #yosys
sklv has quit [Read error: Connection reset by peer]
sklv has joined #yosys
<keesj>
ZipCPU: I now better uderstand why you asked about my serial to register mapping project.
<keesj>
I never user chipscope so far (i remember scanning some jtag scan chain but somewhere I must have run into problems) This was on a Digilen Basys2 Xilinx Spartan-3E FPGA.
proteusguy has quit [Remote host closed the connection]
sklv has quit [Quit: quit]
GuzTech has joined #yosys
proteusguy has joined #yosys
emeb_mac has quit [Quit: Leaving.]
emeb has quit [Quit: Leaving.]
oldtopman has quit [Ping timeout: 252 seconds]
oldtopman has joined #yosys
tpb has quit [Remote host closed the connection]
tpb has joined #yosys
shapr has quit [Ping timeout: 264 seconds]
janrinze has quit [Ping timeout: 264 seconds]
xa0 has quit [Ping timeout: 276 seconds]
Chobbes has quit [Ping timeout: 276 seconds]
xa0 has joined #yosys
janrinze has joined #yosys
shapr has joined #yosys
shapr is now known as Guest12920
xa0 has quit [Ping timeout: 276 seconds]
lok[m] has quit [Ping timeout: 260 seconds]
swick has quit [Ping timeout: 260 seconds]
lok[m] has joined #yosys
swick has joined #yosys
xa0 has joined #yosys
Chobbes has joined #yosys
FabM has quit [Read error: No route to host]
FabM has joined #yosys
quigonjinn has quit [Remote host closed the connection]
AlexDaniel has joined #yosys
proteusguy has quit [Remote host closed the connection]
proteusguy has joined #yosys
proteusguy has quit [Ping timeout: 240 seconds]
eduardo__ has joined #yosys
eduardo_ has quit [Ping timeout: 256 seconds]
xrexeon has joined #yosys
cemerick_ has joined #yosys
cemerick has joined #yosys
cemerick_ has quit [Ping timeout: 260 seconds]
pie_ has joined #yosys
promach_ has joined #yosys
proteusguy has joined #yosys
X-Scale has joined #yosys
seldridge has joined #yosys
promach__ has joined #yosys
seldridge has quit [Ping timeout: 260 seconds]
seldridge has joined #yosys
[X-Scale] has joined #yosys
X-Scale has quit [Ping timeout: 240 seconds]
[X-Scale] is now known as X-Scale
rqou has quit [Remote host closed the connection]
rqou has joined #yosys
GuzTech has quit [Quit: Leaving]
seldridge has quit [Quit: WeeChat 1.4]
seldridge has joined #yosys
AlexDaniel has quit [Ping timeout: 260 seconds]
<promach__>
for the smt_step, how do I reference it in assert() ?
<ZipCPU>
promach__: Give me a little more back ground ... what are you talking about?
<ZipCPU>
Ah ... to my knowledge, you don't reference the smt_step number in an assertion. You can create your own counter to reference if you would like, but you can't reference that one.
<promach__>
ok, I see. Thanks
X-Scale has quit [Ping timeout: 256 seconds]
digshadow has left #yosys [#yosys]
seldridge has quit [Ping timeout: 276 seconds]
promach__ has quit [Ping timeout: 240 seconds]
X-Scale has joined #yosys
pie__ has joined #yosys
ralu has quit [Ping timeout: 264 seconds]
pie_ has quit [Ping timeout: 264 seconds]
ralu has joined #yosys
seldridge has joined #yosys
GuzTech__ has joined #yosys
dys has joined #yosys
sklv has joined #yosys
digshadow has joined #yosys
jkiv has joined #yosys
zkrx has quit [Read error: Connection reset by peer]
zkrx has joined #yosys
xerpi has joined #yosys
cemerick has quit [Ping timeout: 260 seconds]
jkiv has quit [Ping timeout: 255 seconds]
GuzTech__ has quit [Ping timeout: 264 seconds]
xerpi has quit [Quit: Leaving]
pie__ has quit [Remote host closed the connection]