<ZipCPU>
I've spent the whole day trying to write proofs for AXI components and masters.
<ZipCPU>
The more I work with AXI, the more I like and love WB.
<cr1901_modern>
Funny I know most ppl who think the opposite
<cr1901_modern>
I do wish WB permitted single single-cycle xfers
<cr1901_modern>
(sic)
<ZipCPU>
??
<ZipCPU>
Doesn't it?
<cr1901_modern>
ZipCPU: I don't know, does it :P?
<cr1901_modern>
Does pipelined WB allow a cycle to stop in a single cycle?
<cr1901_modern>
s/cycle to stop/single xfer to complete/
<ZipCPU>
You mean, the ACK is returned on the same cycle as the STB request?
<cr1901_modern>
yes
<ZipCPU>
Yes, it does.
<ZipCPU>
That's one of the bugs in my wishbone formal presentation that ... I haven't had the chance to go back and fix.
<cr1901_modern>
Well that makes my life easier if that works...
<ZipCPU>
The spec says explicitly that a slave could hold ACK high if it wanted to in a single component system.
<cr1901_modern>
But can a master finish the xfer by checking ACK in the same cycle it sends STB
<ZipCPU>
Yes.
<cr1901_modern>
okay that makes my life easier then
<ZipCPU>
Are you building WB components?
<cr1901_modern>
Nah, just a thought experiment: hypothetical CPU that comes with an i-cache but leaves the d-cache off >>
<ZipCPU>
Heh ... you are describing the ZipCPU ... I have yet to install a D-Cache.
<cr1901_modern>
but for consistency, the data bus is WB compatible and a user is free to attach a WB memory (classic) or a WB cache (master checks ACK in the same cycle as STB)
<cr1901_modern>
ZipCPU: In this case I would like to experience the pain of doing it myself :)
<ZipCPU>
Well ... what's going to kill your idea is that access to block RAM in most architectures requires a clock.
<ZipCPU>
The other problem you have is any time you try to connect more than just a single peripheral. The interconnect, in my personal experience, tends to consume more clocks than I wish to give to it.
<cr1901_modern>
why would the interconnect itself consume clocks? Is it not combinational except for latching read values?
<ZipCPU>
Well ... if it isn't consuming clocks, then its slowing down your maximum clock rate.
<cr1901_modern>
Ahh I guess you can do that, but adding latency to the interconnect doesn't really sit well w/ me either
<ZipCPU>
I've needed to create interconnects that have consumed .. up to several clocks for the speeds I'm trying to operate at.
<cr1901_modern>
I'd need to see an example of what you mean