clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> ZipCPU: I do not understand why need to replicate the 10K timestep for each bit. It should have been be able to be proved by induction
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<cr1901_modern> thoughtpolice: It does support multiple clock domains
<cr1901_modern> That's what the clk2dfflogic pass is for... and you might even need it anyway with a single clock domain
<cr1901_modern> depends on whether you pissed off the solver or not
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<ZipCPU> Hmm ... I'm testing it across multiple clock domains and coming across some strange bugs.
<ZipCPU> Let me see if I can create a (non-proprietary, sigh) test case.