clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<wsm_> I have downloaded and built yosys
<wsm_> I have scanned the documentation
<wsm_> I want to go down the chain and create a verilog system for psoc5
<wsm_> Here are my questions:
<wsm_> 1) What should I do to yosys to make it work with PSOC 5? (what are the pinch points)
<wsm_> 2) how would I modify Arachne-pnr to accomodate the Psoc 5?
<wsm_> PSoC 5 uses registers rather than bit mat for fabric
<wsm_> Therefore, I expect to have to do an intermediate fake bitmap fabric and run an additional bit of code to turn it into whatever is required
<wsm_> for the psoc 5 to put the bits into the registers.
<wsm_> Any suggestions as to where to start?
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<awygle> wsm_: I would start with writing a Yosys techlib for psoc 5
<awygle> Don't worry about PAR until you get synthesis working
<eduardo_> wsm_.: hi ,
<eduardo_> wsm_: There is one guy at ##openfpga working on reverse engineering the PSOC5
<eduardo_> I would suggest you to ask there.
<eduardo_> they already made good progress.
<pointfree> At the moment I'm working on characterizing the limits of psoc5lp routing flexibility and I think I have a general rule, but I need to test it out a bit more.
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<pointfree> a good tool should take advantage of the available flexibility.
<awygle> pointfree: do you think that your ongoing work will affect synthesis, or only placement and routing?
<pointfree> awygle: synthesis as well. The routing fabric supports AND and OR http://www.psoctools.org/logic-in-routing-fabric-without-plds.html (btw, ...I'm using those AND's and OR's to characterize the flexibility).
<pointfree> I'm entertaining the idea of using synthesis for the routing not just the plds.
<awygle> pointfree: ah, interesting
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<wsm_> Ok. Writing a Yosys techlib. Sounds like pointfree needs to give me pointers
<wsm_> Where do I read about techlib?
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<rqou> wsm_: you should join us over in ##openfpga
<rqou> as for your actual question, you read the existing techlibs
<rqou> afaik greenpak4 and ice40 are probably the most complete (but not the most simple)
<rqou> the most simple is probably gowin, but i don't know how usable it is
<rqou> note that all of these are LUT architectures
<rqou> the only PLD architecture is the not-yet-complete coolrunner2 one
<rqou> (disclaimer: coolrunner2 code written by me)
<wsm_> rqou: thank you.
<wsm_> Yes, Finally figured out was pld architecture AND/OR matrix. Saw that a year or two ago, finally making some sense.
<wsm_> will join at ##openfpga
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