<awygle>
That makes sense, because an array of regs is a memory. When you say "stops working" what do you mean? Can you post the non working code as well?
<mattvenn>
the line commented out is the one that doesn't work
<mattvenn>
by doesn't work I mean the LEDs don't show the ADC data
<awygle>
So you're just commenting that line back in? That's the only change you're making?
<mattvenn>
comment out the line above, and comment in the line below
<awygle>
And you're running on hardware without simulation?
<mattvenn>
the adc.v had a testbench, which simulated and ran fine
<mattvenn>
as I need 4 of these running together I used the genvar and changed the single register to an array
<mattvenn>
that's when I found this issue
<awygle>
Frankly I'm surprised that compiles at all, and I think you have the standard confusion about reg. Reg doesn't automatically produce a register - it just means that you can assign to it in an always block. To register the output of your ADC module you will need to use the wire, then make an always @(posedge clk) block where you assign to the registers.
<mattvenn>
the output of the adc is a register, so the data is already registered
<awygle>
I highly suggest running in Icarus or Verilator before going straight to hardware, especially with Yosys. Yosys doesn't try very hard to protect you from invalid code, so I always at least run verilator --lint-only
<mattvenn>
though I did also try an always block to register the data
<mattvenn>
yes I use both
<mattvenn>
though veriator showed me some weird stuff when i tried it on top.v
<awygle>
So, if your output is already registered, and your wire solution works, what are you trying to accomplish?
<mattvenn>
I just want to understand what's happening
<mattvenn>
I've only just started using yosys show, and not seen the memrd block before. When it's inferred my design doesn't work
<mattvenn>
so I was wondering what it was and if anyone has experienced issues with it
<mattvenn>
if I don't use the generate, and only have one adc, the register version works
<awygle>
That is frankly kind of weird. Maybe someone else has a better idea of what's going on in detail.
<mattvenn>
only if I use a genvar do I get the memrd, and the design stops working
<mattvenn>
thanks for your help though ;)
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<ZipCPU>
No, it's not all that wierd ... it's matching my own experiences.