pie_ has quit [Read error: Connection reset by peer]
pie___ is now known as pie_
qu1j0t3_ has joined #yosys
qu1j0t3 has quit [Ping timeout: 248 seconds]
<cr1901_modern>
Are you using the clk2dfflogic pass?
<ZipCPU>
You mean clk2fflogic?
<cr1901_modern>
yes that
<ZipCPU>
I took it out and still had problems.
<cr1901_modern>
Of course... it's never easy lol
<ZipCPU>
or should I rather say ... I took it out had still had the *same* problems.
qu1j0t3_ is now known as qu1j0t3
pie_ has quit [Remote host closed the connection]
pie_ has joined #yosys
pie_ has quit [Remote host closed the connection]
digshadow has quit [Ping timeout: 240 seconds]
proteusguy has quit [Ping timeout: 246 seconds]
digshadow has joined #yosys
digshadow has quit [Ping timeout: 248 seconds]
proteusguy has joined #yosys
<awygle>
ZipCPU, cr1901_modern: have either of you done anything with the "assert property" style of assertions?
<cr1901_modern>
awygle: Not much, tbh
<awygle>
afaict yosys is happy enough to do "assert property" but doesn't support |-> or |=> and you can't specify a clock
jhol has quit [Quit: Coyote finally caught me]
qu1j0t3 has quit [Ping timeout: 248 seconds]
qu1j0t3 has joined #yosys
<awygle>
do i understand correctly that when calling the "sat" command from within yosys, yosys itself does the computation, but when calling yosys-smtbmc SMT2 is generated and fed to (yices/z3/etc)?
pie_ has joined #yosys
proteusguy has quit [Remote host closed the connection]
proteusguy has joined #yosys
nrossi has joined #yosys
mbuf has joined #yosys
pie_ has quit [Remote host closed the connection]
pie_ has joined #yosys
pie_ has quit [Quit: Leaving]
<cr1901_modern>
I believe so, but I've never used yosys' SAT solver
sklv has quit [Remote host closed the connection]
sklv has joined #yosys
sklv has quit [Remote host closed the connection]
awygle has quit [Ping timeout: 240 seconds]
sklv has joined #yosys
sklv has quit [Remote host closed the connection]
sklv has joined #yosys
qu1j0t3 has quit [Ping timeout: 248 seconds]
dys has quit [Ping timeout: 248 seconds]
dys has joined #yosys
qu1j0t3 has joined #yosys
m_t has joined #yosys
sklv has quit [Ping timeout: 248 seconds]
sklv has joined #yosys
proteusguy has quit [Remote host closed the connection]
ZipCPU|Laptop has quit [Quit: Transitioning to a lower energy state]
proteusguy has joined #yosys
<ZipCPU>
awygle: I've only come across a single example that used it, so, No, I haven't used the "assert property" style at all.
<ZipCPU>
and even that one example didn't declare the property, it just did more of an "assert property (expression);" type syntax.
<ZipCPU>
I'm still not certain when to use it versus something else.
sklv has quit [Remote host closed the connection]
sklv has joined #yosys
mbuf has quit [Quit: Leaving]
AlexDaniel has quit [Ping timeout: 258 seconds]
stoopkid has quit [Quit: Connection closed for inactivity]
<thoughtpolice>
I think actual SystemVerilog has some important subtle points, but in Yosys, IIRC, 'assert property (foo);' is just a convenient shorthand for 'always @* assert(expression);'
eduardo__ has joined #yosys
eduardo_ has quit [Ping timeout: 240 seconds]
rah has quit [Ping timeout: 258 seconds]
rah has joined #yosys
rah has quit [Client Quit]
m_t has quit [Quit: Leaving]
* shapr
hops randomly
* ZipCPU
wonders why shapr is feeling so hoppy today.
<shapr>
I'm trying to find the parts list for this Radio Shack 1969 neon relaxation oscillator project
<shapr>
and I'm looking into which ice40 chips have the easiest profile to hand solder
<shapr>
since I want to start designing PCBs
<shapr>
ZipCPU: how you doin today?
<ZipCPU>
I'm cursing Altera today. ;)
<qu1j0t3>
oh?
<ZipCPU>
I have a wonderful FPGA design that just needs to work with an Altera Cyclone-5 board, communicating between the hard ARM processor and the FPGA.
<ZipCPU>
That's all I want right now ...a memory mapped connection to the FPGA.
<ZipCPU>
And I've been digging through manuals, examples, etc., struggling to get this going.
<qu1j0t3>
shapr: curious about the oscillator project. off topic for here but is there somewhere else you're discusisng this?
<shapr>
qu1j0t3: uh, you could jump on my personal chat channel #scannedinavian
<qu1j0t3>
yeah why not!
<ZipCPU>
Why can't they be as easy to use as Xilinx? (I'm sure the Altera designer in my position would be saying the same thing about Altera ...)
<qu1j0t3>
thanks
digshadow has joined #yosys
awygle has joined #yosys
digshadow has quit [Ping timeout: 264 seconds]
proteusguy has quit [Ping timeout: 252 seconds]
<awygle>
Thanks ZipCPU
befedo has joined #yosys
digshadow has joined #yosys
SMDhome has quit [Ping timeout: 258 seconds]
SMDhome has joined #yosys
proteusguy has joined #yosys
digshadow has quit [Ping timeout: 258 seconds]
digshadow has joined #yosys
nrossi has quit [Quit: Connection closed for inactivity]