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<bubble_buster>
so what are tradeoffs between wishbone bus and axi? simplicity? licensing/freeness?
<awygle>
bubble_buster: simplicity is a matter of perspective, but many feel WB is simpler than AXI
<awygle>
certainly WB is an open standard while AXI is a licensed product of ARM (although iiuc the license is free)
<awygle>
for my own part, i'd say the major tradeoff is "which existing body of IP do i want to integrate more easily with, the open source community (WB) or Xilinx (AXI)?"
<awygle>
also Altera has their own thing which i think is called Avalon
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<awygle>
has anyone done any equivalence checking with Yosys? ZipCPU, maybe?
<awygle>
thoughtpolice? i recall you talking about miters once upon a time
<thoughtpolice>
awygle: I was not using Yosys, it was in a different domain (formal h/w method tools, applied to cryptographic code), but yes it was in a broad sense just equivalence checking. SymbiYosys -- at some point in the future -- will probably have a mode to help with this, but I haven't used the 'raw' yosys support for this. It looks pretty easy though at a glance from some slides
<thoughtpolice>
awygle: see slide 34 -- http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf -- basically, just make two modules, use 'equiv_make' to create a new circuit from two inputs (e.g. synthesize a miter, since it's obviously very easy to do so), and use various equiv_* commands
<awygle>
thoughtpolice: thanks. Yeah I'm trying that but not getting equiv... Even though I'm comparing the same circuit output with write_verilog and write_json... I'll try some other stuff
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<awygle>
ah, i needed equiv_induct. that makes sense, given that i had sequential logic in my modules
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