clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<bubble_buster> anybody considering being a Google Summer of Code mentor organization? ZipCPU? clifford?
<ZipCPU> I've never done that before. Would you be interested in it in some fashion if I chose to do so?
<bubble_buster> maybe. I'm interested in working on the tools more than using them, so, yes, if it was a project like that
<bubble_buster> I like the stuff you're doing to but idk about doing a whole GSoC project like that
<ZipCPU> Well, ok, sure. Clifford currently has a couple of understudies, so he'd really be the person to talk to.
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<mattvenn> just found out that in yosys, you can type help $reduce_or or help $pmux to get info on those mappings
<mattvenn> and help $pmux+ will get you the verilog
<mattvenn> very useful!
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<ZipCPU> Ever thought of trying the write_verilog function?
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<mattvenn> @zipcpu didn't even know it existed!
<mattvenn> so far I've learnt read_verilog, proc, opt, show and now help
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<ZipCPU> One of the recent capabilities I found was "opt -share_all". Now that I've learned it, I'm tending to use it everywhere.
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<awygle> What's the benefit of -share_all over standard opt?
<ZipCPU> If you have two separate instantiations of identical logic, -share_all forces them to share resources
<ZipCPU> I discovered this option while trying to find a way to solve a formal problem.
<awygle> Ah. So it is like link time optimization? It causes the optimizer to look past module boundaries?
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<ZipCPU> Yeah, sort of like that.
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