clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZipCPU> promach_: Didn't we discuss what induction was before?
<ZipCPU> Induction starts with all of your variables/registers taking on random values.
<ZipCPU> That large space of all possible values is then reduced by the assumptions and assertions you've made.
<ZipCPU> Those random registers are then propagated forward, and again restricted by the assumptions and assertions that follow.
<ZipCPU> After a given number of steps that you specify, the induction step tries to see if it can break any assertions.
<ZipCPU> In other words ... there is no initial statement during induction. Consider instead that your design is "started" millions of clocks after the initial statement, and induction looks at only N of the clocks following.
<ZipCPU> If it can find a valid path through those N clocks, it *then* tries to find an invalid transition on clock N+1.
<ZipCPU> Perhaps what you want to do is to assert, always @(*) begin assert(cnt <= 88); if (!has_been_enabled) assert(cnt == 0); end
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<ZipCPU> promach promach_: Made any progress? Did last night's explanation make sense to you? It's ... sort of a fundamental property of formal verification types of stuffs, and ... something you need to learn if you intend to use those methods.
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<promach> ZipCPU: I am working on it now
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<Kooda> Hi there! I’m back with my odd problems. :x
<Kooda> I’ve been looking at a piece of code for a few days and didn’t understand what was wrong with it… Just for the sake of it, I tried it in IceCube instead of with IceStorm… and it works. :/ Could someone help me find what’s wrong? :x
<Kooda> There might be something I’m missing, or I found a bug in one of the icestorm tools. :x
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<ZipCPU> Kooda: What's it supposed to do?
<Kooda> Display stuff on a VGA monitor.
<Kooda> This is the entire program: https://www.upyum.com/cgit.cgi/vgatest/tree/vgatest.v
<ZipCPU> Hmm ... okay.
<Kooda> I can ever reduce it to just outputing the color red, for example, and it doesn’t work. But it works with color blue.
<Kooda> even*
<Kooda> What I mean by work is: the monitor shows the expected image, and not an error.
<Kooda> Unfortunately I don’t have tools like a logic analyzer or oscilloscope…
<ZipCPU> Then you are in luck today ... ;)
<ZipCPU> I just posted a VGA testing program based upon Verilator.
<ZipCPU> You can find it in https://github.com/ZipCPU/vgasim
<Kooda> Haha :D
<ZipCPU> While the code is written in Verilog, the test bench runs on a gtkmm enabled platform. (i.e., my Linux desktop, but probably Windows as well)
<ZipCPU> That'll allow you to get the logic analyzer traces you want--since it all runs in Verilator.
<Kooda> I’ve been meaning to write that at some point. ^^
<ZipCPU> Further ... you'll be able to visually "see" the results in a window on your computer.
<Kooda> The problem is, I won’t know why the result is different with icestom and icecube.
<Kooda> I use the exact same verilog code.
<ZipCPU> What error were you getting from icecube?
<Kooda> None
<Kooda> I don’t get any error from any tool.
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<ZipCPU> So what was the problem then?
<Kooda> But when I compile and upload my design with icecube, the animation shows on the monitor. When I compile and upload my design with icestorm, the monitor errors out.
<ZipCPU> Let me guess that the problem is the PLL. Are you watching the PLL's lock output to see if it is locked?
<Kooda> I’m not
<ZipCPU> You might wish to dump the locked output to an LED or something.
<Kooda> But shouldn’t it work after some time anyway?
<Kooda> Oh, I can do that.
<Kooda> What’s very strange is that, depending on the color I try to output (only with the icestorm toolchain) I get the error from the monitor, or the right color. With IceCube every color I tried works fine.
<ZipCPU> That might suggest you've got a bug in the pin mapping.
<Kooda> I use the same pin mapping file with both toolchains.
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<awygle> Kooda: some things to try - check icetime to see if you make timing. Compare the synthesized results from the two toolchains. Maybe dump the synthesized output from Yosys and feed it to icecube to see if you can narrow down the location of the error
<awygle> Definitely make sure your PLL is locking, and if you do figure out where the issue is, let us know!
<ZipCPU> Kooda: Neat pattern, https://imgur.com/a/m6lVY
<ZipCPU> Oops, 3-bit color, not four ... try this link: https://imgur.com/VIbHUaM
<ZipCPU> Hey, that's cool ... the color and pattern changes over time as well ...
<ZipCPU> Let me speed it up by turning off the .vcd trace generation ...
<Kooda> ZipCPU: yep, that’s what shows on my monitor as well. :3
<Kooda> Just a classic animated xor pattern.
<ZipCPU> Sure! although .... I must not be familiar with a classic animated xor pattern, since this is the first time I've seen this one.
<Kooda> awygle: I will try, but I’m very new to the whole Verilog and FPGA thing.
<ZipCPU> Kooda: Do you think the video simulator would help you at all? I mean ... I could send you a pull request with my changes and additions if you wanted ...