clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach_> ZipCPU: is temporal induction very difficult to pass ?
<promach_> I am very worried when I passed my temporal induction for UART with Tx and Rx together
<promach_> seems like I do not have enough assert()
<ZipCPU> Is temporal induction "difficult" to pass? Might depend upon your code.
<ZipCPU> Temporal induction is "required", though, or you haven't fully verified your code.
<ZipCPU> Did you read my introduction to formal methods?
<ZipCPU> I think I explain through some of what you are struggling with.
<ZipCPU> I mean, if you are comparing induction to BMC, they I would say your comparison is ill formed. The two together constitute a formal verification of your design. One by itself is mostly meaningless.
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