clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> Do you guys have any comments about https://github.com/promach/UART/blob/development/rtl/test_UART.v#L40 ? I have Unreached cover statement at ../rtl/test_UART.v:40. I am not sure what I have missed though
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<ZipCPU> promach: Perhaps you'd like to try simulation instead. That'll help show you what's going on.
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<cr1901_modern> Or do what I did: https://gist.github.com/cr1901/a445ef31281e67a0cf286e149deaac41 (Disclaimer: these are unorganized notes. They are meant to be part of a future blog post)
<cr1901_modern> Also, you _must_ do the prerequisites _in order_
<cr1901_modern> this is how I was able to get started with formal methods, and is the path that worked for me
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