<promach>
reg[$clog2(NUMBER_OF_STATES*CLOCKS_PER_STATE):0] cnt; // to track number of clock cycles between assertion of 'enable' signal and 'data_is_valid' signal
<promach>
ZipCPU: do you have any way to assert that 'cnt' starts from zero even during induction test ?
<ZipCPU>
As for ways to assert 'cnt' starts from zero during induction .... that's not how induction works.
<ZipCPU>
Instead, try asserting a value of 'cnt' that matches the surrounding environment, forcing it to have the right value--despite not starting from zero.
<ZipCPU>
Using those bindings, #yosys has support for more verilog features as well as VHDL.
<ZipCPU>
It also has support for the full system verilog property sets.
<promach>
but is it usable ?
<ZipCPU>
Only problem is .... Verific is commercial (not open source) software.
<ZipCPU>
Usable? I am told so. I just haven't used it myself.
<promach>
it is only free for 30 days, then verific is no longer usable for free
<ZipCPU>
I might recommend you learn the basics before trying something like Verific, though. That way you'd get the most out of a 30day trial.
<promach>
true
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<promach>
ZipCPU: to be frank, there is just not only one bug left
<promach>
it is far from working
<ZipCPU>
If you know it's that broken, why don't you rebuild it from the ground up in a way that won't nearly be so broken?
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<ZipCPU>
promach: The purpose of test benches and formal verification processes are not to help you write good code, but rather to help you clean up any bugs in what should already be good code.
<ZipCPU>
If you know your code has problems, don't continue to test-bench or formally verify the code, fix the code--then come back and test and prove it.
<promach>
ZipCPU: ok, I would say my Rx contributes all the problems mostly