<promach>
For sequence checking, is there any other specifiers that do beyond what $past could do ? for example, checking the past 'N" events ?
<awygle>
promach: in system verilog $past can take an argument which says how many clocks back to check. I don't know if Yosys supports it, I'd recommend you try it and find out
<promach>
awygle: you mean $past(variable, N) ?
<awygle>
Yes
<ZipCPU>
awygle: Yosys formal supports it
<promach>
what about event sequence check ?
<promach>
event A happens BEFORE event B ?
<promach>
that is not how $past() is designed for, I suppose ?
<promach>
There must be some other specifiers that can do this check
<ZipCPU>
event_A is just an expression describing whatever event you were looking for.
<ZipCPU>
It may or may not be an expression.
<ZipCPU>
I mean ...
<ZipCPU>
It may or may not be an register.
<promach>
A <= (A) || (event_A); --> this does not look alrght to me at first sight
<ZipCPU>
Why not?
<ZipCPU>
You want to know if (event_A) has taken place in the past. A holds that information. If event A has taken place, it needs to be sticky (unless you want to reset it later ...).
<ZipCPU>
Hence (A) (meaning A has already taken place) || (a logical OR) (event_A) (meaning that event A is currently taking place now).
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<promach>
does the hamster's tinytx code use formal verification tool ?
<promach>
ZipCPU
<ZipCPU>
You tell me.
<ZipCPU>
You're the one who has been digging into it.
<ZipCPU>
yosys uncovered a bug in VHDL? You mean ... you are using the proprietary extension to yosys?
<promach>
no
<promach>
give me a moment
<promach>
let me change the question perspective
<promach>
For UART in ASIC, how would you handle the initial reset circuitry since the receiver has no prior knowledge about the transmission control signals within the transmitter ?
<ZipCPU>
Why are you asking about ASICs?
<promach>
because of the initial reset which is available in FPGA
<promach>
initial global reset circuitry
<ZipCPU>
Sure, so ... why are you asking about ASICs?
<promach>
that is to learn how UART is implemented as hardcore
<ZipCPU>
Who's asking you to ask?
<promach>
huh ?
<ZipCPU>
Judging by all you've told me ... you don't have the cash to afford doing ASIC work. So .... who are you asking on behalf of?
<promach>
no, it is all for my learning purpose
<ZipCPU>
Then learn how to build one on an FPGA first.
<promach>
ASIC work is interesting, I would love to dig more into it
<promach>
sure
<ZipCPU>
ASIC works is *EXPENSIVE*. If you don't have a couple million $USD in your pocket, then you have no reason being interested.
<ZipCPU>
That said, a UART receiver should naturally reset after one character (or so) of the line being high.
<promach>
so, UART receiver ignores whatever being received in the initial 1 character time ?
<ZipCPU>
Maybe, maybe not. Did I say just one character? After a couple idle characters, it's all set to go.
<promach>
that is one possible solution :)
<ZipCPU>
Well ... try building another solution and tell us how it works then.
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