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<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 98497b2 - build.dsl: require a dict for extras instead of a stringly array.
01:58
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 268fe63 - build.res: simplify. NFC.
01:58
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark fb01854 - build.{res,plat}: propagate extras to pin fragment factories.
01:59
<
_whitenotifier-3 >
[nmigen] whitequark closed issue #72: In nmigen.build, extras should probably be a dict, not an array -
https://git.io/fjECv
02:26
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark b64a312 - hdl.ir: accept expanded (kind, name, value) tuples in Instance.
02:26
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark b8a61ed - hdl.dsl: allow adding submodules with computed name, like with domains.
02:55
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark c6a0761 - hdl.ir: accept LHS signals like slices as Instance io ports.
02:55
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark dc17d06 - vendor.fpga.lattice_ice40: instantiate SB_IO and apply extras.
02:55
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark f417725 - build.res: if not specified, request resource #0.
03:26
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03:36
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 3327dea - vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files.
03:36
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark c30617f - lib.io: allow Pin(xdr=0), representing a combinatorial I/O buffer.
03:37
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark cd6488c - build.res: allow requesting raw ports, with dir="-".
03:37
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 9ba2efd - build.{res,plat}: use xdr=0 as default, not xdr=1.
03:51
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<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 1eee7cd - lib.io: allow dir="oe".
04:43
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 6fae06a - build.{dsl,plat,res}: allow dir="oe".
05:35
<
_whitenotifier-3 >
[nmigen] whitequark opened issue #78: Implement XDR buffer factories for all platforms -
https://git.io/fjEMr
06:19
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07:45
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark a1940c5 - hdl.rec: unbreak hasattr(rec, ...).
07:45
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark b42043f - lib.io: add i_clk and o_clk to pin layout with xdr>=1.
07:45
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 185abb4 - vendor.fpga.lattice_ice40: implement SDR and DDR I/O buffers.
07:45
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09:25
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 3116d4a - vendor.fpga.lattice_ice40: allow instantiating SB_GB_IO via extras.
09:25
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 41adcc3 - vendor.fpga.lattice_ice40: implement differential input buffers.
09:25
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 1670800 - vendor.fpga.lattice_ice40: implement differential output buffers.
09:27
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09:28
<
whitequark >
sb: key2: jfng: every aspect of iCE40 with yosys/nextpnr is done, i think
09:28
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 639e64c - vendor.fpga.lattice_ice40: implement differential output buffers.
09:28
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09:30
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whitequark >
hmm, let me add back connectors and it'll be largely done, i think
09:33
<
TD-Linux >
nmigen (using the compat layer) seems to error out that my TSTriple is never elaborated. I think this is because I only ever get_tristate() on it in synth, not simulation. is there a way to get around this?
09:38
<
whitequark >
it's not an error
09:39
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 4c443a7 - compat.fhdl.specials: TSTriple is not an elaboratable.
09:40
<
TD-Linux >
aha thanks
09:49
<
TD-Linux >
neato. with that change, sim works unmodified. (with some driverconflict warnings that were intentional in the original migen)
09:50
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whitequark >
excellent
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15:02
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark a013eb1 - build.dsl: add support for connectors.
15:02
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark ed64880 - build.{plat,res}: add support for connectors.
15:05
<
_whitenotifier-3 >
[nmigen] whitequark opened issue #79: Add a library of connector layouts, too -
https://git.io/fjEbr
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15:38
<
_whitenotifier-3 >
[nmigen] sbourdeauducq commented on issue #79: Add a library of connector layouts, too -
https://git.io/fjENE
15:41
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark f351e2b - vendor.ice40_hx1k_blink_evn: add (some) connectors.
15:41
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 7c5461d - vendor.icestick: add connectors.
15:41
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 2ca0834 - vendor.tinyfpga_bx: add connectors.
15:44
<
_whitenotifier-3 >
[nmigen] whitequark commented on issue #79: Add a library of connector layouts, too -
https://git.io/fjEN1
15:46
<
_whitenotifier-3 >
[nmigen] whitequark commented on issue #79: Add a library of connector layouts, too -
https://git.io/fjEND
15:54
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16:00
<
_whitenotifier-3 >
[nmigen] mithro commented on issue #79: Add a library of connector layouts, too -
https://git.io/fjEAk
16:01
<
mithro >
whitequark: I know way too much about pmod and own like a bazillion pmod devices, if you have any questions or anything, please do reach out
16:01
<
_whitenotifier-3 >
[nmigen] whitequark commented on issue #79: Add a library of connector layouts, too -
https://git.io/fjEAt
16:02
<
cr1901_modern >
I started a set of Pmod abstraction classes, but I didn't like the way they turned out
16:02
<
whitequark >
it's honestly pretty easy
16:03
<
cr1901_modern >
Probably make a pmod-gpio, pmod-spi, pmod-multiple-conn, pmod-i2c, pmod-6pin, pmod-12pin class
16:03
<
cr1901_modern >
oh and "pmod 6pin but it spans over 2 connectors"
16:07
<
_whitenotifier-3 >
[nmigen] mithro commented on issue #79: Add a library of connector layouts, too -
https://git.io/fjEA0
16:07
<
_whitenotifier-3 >
[nmigen] whitequark commented on issue #79: Add a library of connector layouts, too -
https://git.io/fjEAE
16:07
<
whitequark >
simple as that
16:08
<
whitequark >
the 7 segment one would just have pmod0 and pmod1 arguments instead of a single pmod argument
16:09
<
_whitenotifier-3 >
[nmigen] whitequark commented on pull request #76: Added TinyBX gpio , fix on programmer. -
https://git.io/fjEAa
16:10
<
mithro >
whitequark: Yeah something like what you showed there could work, I'll probably be happy with /anything/ that was "upstream" that people use
16:10
<
cr1901_modern >
LGTM. I would also add a "top" and "bottom" arg to the 7-seg one since either set of 6 pins would work for the 7seg pmod (split across 2 pmods)
16:10
<
cr1901_modern >
What's the "*" in "PmodSPIResource(name, number, *, pmod, extras):" for?
16:11
<
_whitenotifier-3 >
[nmigen] mithro commented on issue #79: Add a library of connector layouts, too -
https://git.io/fjEA6
16:19
<
_whitenotifier-3 >
[nmigen] mithro commented on issue #79: Add a library of connector layouts, too -
https://git.io/fjEA9
16:29
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16:31
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 0fa45b5 - vendor.board: extract package.
16:31
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 3d04122 - examples: reorganize into examples/basic and examples/board.
16:32
<
whitequark >
cr1901_modern: you can't mention pmod as a normal argument
16:32
<
whitequark >
only keyword argument
16:32
<
whitequark >
so you can't do PmodSPIResource("spiflash", 0, 1)
16:32
<
whitequark >
because it's confusing
16:33
<
cr1901_modern >
ahhh
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16:50
<
_whitenotifier-3 >
[m-labs/nmigen] whitequark 6426b90 - vendor.conn.pmod: implement.
16:50
<
_whitenotifier-3 >
[nmigen] whitequark closed issue #79: Add a library of connector layouts, too -
https://git.io/fjEbr
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<
TD-Linux >
how do I debug an "object cannot be elaborated" error?
21:29
<
TD-Linux >
hmm seems to be an issue with the compat layer. "Module" is not elaboratable
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