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[m-labs/nmigen] whitequark 58e39f9 - hdl.mem: coerce memory init values to integers.
03:43
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_whitenotifier-3 >
[m-labs/nmigen] whitequark d2d8c2b - back.rtlil: mask memory init values.
03:43
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[nmigen] whitequark closed issue #93: error message from improper memory initialization -
https://git.io/fjzRP
03:43
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[nmigen] whitequark closed issue #96: negative values in memory initialization -
https://git.io/fjgk0
03:48
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[nmigen] whitequark commented on issue #4: Require signals crossing clock domains to be explicitly marked -
https://git.io/fjgBx
03:54
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_whitenotifier-3 >
[m-labs/nmigen] whitequark 066dd79 - back.pysim: check for a clock being added twice.
03:54
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_whitenotifier-3 >
[nmigen] whitequark closed issue #27: Simulator: adding two clocks to a single domain causes DeadlineError in simulation -
https://git.io/fh6f6
04:06
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_whitenotifier-3 >
[nmigen] whitequark opened issue #97: Bikeshed: conventions for CDC primitives -
https://git.io/fjgRI
04:09
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_whitenotifier-3 >
[nmigen] whitequark opened issue #98: Generated Verilog should be more readable -
https://git.io/fjgRL
04:14
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[nmigen] sbourdeauducq commented on issue #97: Bikeshed: conventions for CDC primitives -
https://git.io/fjgRt
04:45
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[m-labs/nmigen] whitequark ad1a40c - hdl.ast: implement values with custom lowering.
07:03
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07:48
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[nmigen] mithro commented on issue #98: Generated Verilog should be more readable -
https://git.io/fjgER
07:51
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[nmigen] whitequark commented on issue #98: Generated Verilog should be more readable -
https://git.io/fjgEu
07:58
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15:48
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[nmigen] Wren6991 synchronize pull request #40: WIP: Expand and document lib.cdc -
https://git.io/fhxap
15:53
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[nmigen] Wren6991 commented on pull request #40: WIP: Expand and document lib.cdc -
https://git.io/fjg6i
16:08
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[nmigen] Wren6991 synchronize pull request #40: WIP: Expand and document lib.cdc -
https://git.io/fhxap
16:09
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[nmigen] Wren6991 commented on pull request #40: WIP: Expand and document lib.cdc -
https://git.io/fjgik
16:14
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[nmigen] Wren6991 synchronize pull request #40: WIP: Expand and document lib.cdc -
https://git.io/fhxap
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17:53
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[nmigen] jfng opened pull request #99: vendor.xilinx_7series: implement DDR I/O buffers. -
https://git.io/fjgXa
17:56
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[nmigen] codecov[bot] commented on pull request #99: vendor.xilinx_7series: implement DDR I/O buffers. -
https://git.io/fjgXw
18:12
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_whitenotifier-3 >
[nmigen] jfng synchronize pull request #99: vendor.xilinx_7series: implement DDR I/O buffers. -
https://git.io/fjgXa
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