sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 3 commits to master [+0/-0/±6] https://git.io/fjrwV
<_whitenotifier-3> [m-labs/nmigen] whitequark e5e2364 - hdl.{ast,dst}: directly represent RTLIL default case.
<_whitenotifier-3> [m-labs/nmigen] whitequark b1af060 - compat.fhdl.structure: simplify handling of default case.
<_whitenotifier-3> [m-labs/nmigen] whitequark 2f7e523 - compat.fhdl.structure: fix typo.
<_whitenotifier-3> [nmigen] Failure. The Travis CI build failed - https://travis-ci.org/m-labs/nmigen/builds/550569763?utm_source=github_status&utm_medium=notification
<sb0> whitequark: hoes does this guarantee you balanced timing? what about routing delays?
<sb0> whitequark: re. language changes, ok
<whitequark> sb0: when nextpnr gains relative placement constraints i could actually guarantee routing delays too
<whitequark> "place these two LUTs in the same slice"
<whitequark> right now it's not really usable for a variety of reasons
<sb0> okay, but then the two paths from that sllice can take different routes
<sb0> for differential signaling you want very tight matching. i'm not sure if this trick works at all.
<whitequark> sb0: and the whole thing is placed next to the IOB, of course
<whitequark> according to my experiments it does work
<sb0> in what case would you not use the built-in differential buffers?
<whitequark> ice40 doesn't have differential output buffers
<whitequark> it's not really a problem if you're using the IOB register, because if you clock both IOBs from the same GBUF it should happen at pretty much the same time
<sb0> okay. so what about implementing this platform-specific hack for ice40 only instead of requiring some support for it on all FPGAs?
<whitequark> however, there are routing restrictions that make it not always possible
<whitequark> oh, but it's not just ice40
<whitequark> for example, on ecp5, nextpnr currently will not pack an FF into an IOB at all
<whitequark> and diamond sometimes refuses to pack an FF into an IOB, with unclear but obnoxious constraints on it
<sb0> does ecp5 have differential in/out buffers?
<whitequark> yes, both
<sb0> so we don't need the pseudo-differential hack
<whitequark> not on all pins though
<whitequark> i think it's something like all pin pairs on top and bottom banks, and half pin pairs on left and right banks
<whitequark> anyway, that's not really why i use it across the board
<sb0> I worry that implementations for all FPGAs are tedious and won't be properly tested
<sb0> in particular, they will have issues with delay matching between the two pairs
<whitequark> right, but that's not why the ixor and oxor functions are present across all platforms
<whitequark> it's just because when all IOB instantiation code looks roughly the same, it's easier to work with
<whitequark> it makes no sense to abstract things like IOB names etc and use inheritance in this case, so it's mostly copy-paste, and it's just nicer when it's regular
<whitequark> I actually made it the way you want first, and then I needed to make some change to all 4 platform files, and it turned out that when all of them are subtly different, it is very easy to introduce a bug, and miss it during testing
<whitequark> anyway. i'm not married to get_ixor. if you really want to get rid of it, go ahead. but i'd expect that result in more bugs, not less
<whitequark> speaking of bugs I should fix CI
<_whitenotifier-3> [nmigen] whitequark commented on issue #109: ECP5 I/O issues - https://git.io/fjrr6
<_whitenotifier-3> [nmigen] whitequark closed issue #109: ECP5 I/O issues - https://git.io/fjrEH
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<_whitenotifier-3> [nmigen] DurandA commented on issue #107: Using Verilog attribute on Instance - https://git.io/fjro4
<_whitenotifier-3> [nmigen] whitequark commented on issue #107: Using Verilog attribute on Instance - https://git.io/fjroz
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<_whitenotifier-3> [m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fjrKM
<_whitenotifier-3> [m-labs/nmigen] whitequark 6f4e315 - back.pysim: fix scope screwup.
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<_whitenotifier-3> [nmigen] Success. The Travis CI build passed - https://travis-ci.org/m-labs/nmigen/builds/550630193?utm_source=github_status&utm_medium=notification
<_whitenotifier-3> [nmigen] Success. 80.77% (+0.02%) compared to 2f7e523 - https://codecov.io/gh/m-labs/nmigen/commit/6f4e3156d81ada756435651f40ae4f74bb59072b
<_whitenotifier-3> [nmigen] Success. 100% of diff hit (target 80.74%) - https://codecov.io/gh/m-labs/nmigen/commit/6f4e3156d81ada756435651f40ae4f74bb59072b
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<Astro-> zc706 eth has started processing my tx descriptors, but it's not sending any packets, even the stats regs show no changes
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<sb0> hmm disassembling ROSAs is annoying. everything is glued or spot-welded into place
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