sb0 changed the topic of #m-labs to: https://m-labs.hk :: Mattermost https://chat.m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<whitequark> sb0: did you get my email response from 2019-06-03 btw?
<sb0> whitequark: no
<whitequark> sb0: ah, crap, let me resend
<sb0> got a rust program to run with minerva + nmigen + ecp5
<whitequark> excellent
<whitequark> which board and how do you synthesize?
<whitequark> i have most of ecp5 platform support done in nmigen, plus versa platform
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<sb0> versa
<sb0> nix-build -A simplesoc_ecp5 release.nix with nixpkgs ae71c13a
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<sb0> still using the same hack to work around the lack of platform support
<whitequark> ok, i'll try to finish it today
<whitequark> sb0: what is the reason for having separate eth_clocks resource?
<sb0> where?
<whitequark> e.g. arty a7, versa ecp5 in omigen
<sb0> I didn't write this code
<whitequark> i assume it is copied from some code you've written,hm
<whitequark> it's the same on kc705, mixxeo, ...
<sb0> what's unusual about it?
<sb0> *MII PHYs use local clocks
<whitequark> why not just put it in the eth resource itself?
<sb0> because sometimes it's handled by the central clock management in the design
<sb0> e.g. you can use the same PLL to generate the system clock and the GMII TX clock
<whitequark> hmm, is that actually necessary for GMII? GMII uses source synchronous clocking so you can always use an ODDR primitive to do it
<sb0> maybe not with GMII, but RGMII does need some phase tweaking
<whitequark> which also seems more portable than manually routing it
<whitequark> hm, i looked at RGMII too
<whitequark> Data to Clock output Skew (at Transmitter) Typ 0 ps
<sb0> yes, and then there are delay traces on PCB, delay lines inside PHYs with proprietary settings over the PHY registers, etc. the usual hardware snafu
<whitequark> sure
<whitequark> ok, i'll keep that in mind
<whitequark> i still want to see how often the simple behavior (outputting clock with ODDR) will fail but there needs to be an override
<whitequark> sb0: what do you think about adding inverted signals as a part of platform layer?
<sb0> if we already have auto-LVDS, why not
<whitequark> ok, i'll add these then
<whitequark> easy enough
<sb0> max freq for the minerva soc is 102MHz
<sb0> on the non-5g board, not bad
<whitequark> btw the 5g ecp5s are actually "speed grade 9"
<whitequark> they are nominally grade 8 (the highest available and the only one for 5g chips) but in reality they are even faster
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