00:51 <Astro-> zc706: still no tx packets :( oscilloscope on the phy shows me a tx clock and even data, yet the mac tx stats don't change.

00:52 <Astro-> also, the artiq-zynq openocd scripts work well with the zc706.

09:35 <mtrbot-ml> [mattermost] <sb10q> what mac stats? if you get tx clock and data to the phy, what happens to the transmitted packet?

09:36 <mtrbot-ml> [mattermost] <sb10q> whitequark: look for ug903, search for e.g. async_reg

09:37 <mtrbot-ml> [mattermost] <sb10q> whitequark: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug903-vivado-using-constraints.pdf

09:39 <whitequark> sb: interesting, what about false path constraints? that document doesn't seem to say a lot about them

09:47 <mtrbot-ml> [mattermost] <sb10q> by default vivado treats many clock domains are related (coming from the same oscillator) and attempts to analyze all timing paths between them

09:50 <whitequark> sb: ohhh, so the problem is using more than one output of the same MMCM?

10:19 <zignig> whitequark: I transcribed the ISA as I understand it.

10:19 <zignig> https://github.com/zignig/gizmotron/blob/master/v3/inst.py

10:19 <zignig> is broken at the moment ( opcode don't even work )

10:19 <zignig> is a class based method ok ?

10:20 <zignig> cr1901: new simulator as pythonic classes ?

10:20 <whitequark> zignig: that's a whole lot of ceremony for very little use

10:21 <whitequark> 600 lines, probably larger than most of boneless' actual implementatio

10:21 <zignig> how were you going to expose it ?

10:22 <whitequark> something table based from which both the disassembler and assembler can be generated

10:22 <whitequark> no, parsing the tex is not okay either

10:22 <zignig> csv?

10:23 <whitequark> i think i'll write it the way i want to see it once i'm done with the formal spec

10:23 <whitequark> and the actual core implementation

10:23 <zignig> now that I have written it longhand , I think that it can be crunched from the opcodes_v3

11:31 <cr1901> zignig: Not my intent to change the simualtor that much

11:43 <_whitenotifier-3> [nmigen] whitequark opened issue #116: Should memory read ports use domain="comb" or domain=None instead of synchronous=False? - https://git.io/fjoyb

15:36 <Astro-> sb10q: the eth mac has transmitted pkts/bytes counters. they don't change. I don't see the pkt in tcpdump/tshark. continuing to investigate...

16:09 <mtrbot-ml> [mattermost] <sb10q> rjo: what's the status of the gateware/software support for Banker in ARTIQ?