<sb0>
whitequark: do you know a nice way to convert vectorworks to parasolid x_t, or is it TPB + windows VM?
<whitequark>
i've never even touched vectorworks or parasolid
<hartytp>
whitequark: looking at bt/disasm, a lot of code seems to be inlined into main. do you have any pointers for how to fix that/get a better diagnostic
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<whitequark>
hartytp: gdb should be able to show inlined functions in the backtrace
<whitequark>
are you generating/using debug information?
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<whitequark>
hartytp: hm, well you could reduce opt-level or sprinkle #[noinline]
<whitequark>
but i really do wonder why gdb isn't showing you inlined functions in the backtrace
<hartytp>
I seem to get better results without lto
<whitequark>
well yes, lto opens more opportunities for inlining
<whitequark>
same effect as reducing opt-level
<zignig>
whitequark: just looking over the changes to the clocks on the new platform system.
<zignig>
what was the reasoning behind removing the plaform.clock member ?
<zignig>
there does not seem to be a way to get a list of the available clocks on a platform without having them assinged already.
<hartytp>
whitequark: fwiw, here is the kind of bt I'm seeing https://paste.debian.net/1086364/ not sure where to begin with this, anyway, thanks for the help
<whitequark>
zignig: you could not define a clock constraint on something like "eth#0.rx_clk"
<whitequark>
i.e. a subsignal of some resource
<whitequark>
not even easily define, define at all
<whitequark>
it's possible to add some ad-hoc language for specifying subresources, but i decided that instead clocks should be defined by association with their Pin or (if you're not requesting a Pin) raw inout wire
<whitequark>
that you could enumerate (some) clocks was more of an artifact of the system i changed than its purpose
<zignig>
ok I see where you are coming from. So far all my designs are simplistic ( still getting the hang of RTL )
<whitequark>
oMigen had something called default_clk_name and default_clk_period
<whitequark>
I don't like it a whole lot either...
<whitequark>
I might be able to allow requesting clock constraints (if any) from the platform, that would solve half of the problem
<zignig>
Thanks for all you work on nmigen, I'm having fun hacking on my tinybx.
<zignig>
I have a uart ported from your orignal blog post and I am attempting to hook it up to a Boneless-CPU
<whitequark>
that UART isn't especially good btw, it's one of my earliest attempts
<whitequark>
today i would implement it in a completely different (and much simpler) way
<zignig>
it works at 57600 :)
<whitequark>
mostly just a shift register
<whitequark>
and no oversampling
<zignig>
is there going to be a nmigen-cores at some point ?
<whitequark>
probably
<zignig>
:)
<zignig>
I keep on getting "Warning: No clocks found in designWarning: No clocks found in design2 warnings, 0 errors" when I add a boneless CPU to a platformed script
<whitequark>
is your nextpnr up to date?
<zignig>
yep, I've go nextpnr and yosys updating on a cron job...
<whitequark>
archive the build directory and upload it somewhere then
<zignig>
ok
<_whitenotifier-3>
[m-labs/nmigen] whitequark pushed 1 commit to master [+0/-0/±2] https://git.io/fjuXr
<_whitenotifier-3>
[m-labs/nmigen] whitequark b45c511 - build.res: allow querying frequency of a previously constrained clock.
<plaes>
whitequark: regarding m-labs/openocd repository in github, I rebased it against upstream repository and ended up with only two extra commits on-top of master: https://github.com/plaes/openocd/commits/m-labs-master
<whitequark>
plaes: i don't work on that repository
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<cr1901>
whitequark: When trying to run the blinky in this platform file I' m making (by attaching a PMOD): http://ix.io/1L1O, I get the following error: http://ix.io/1L1T
<cr1901>
Would you have any idea what's causing this error?
<cr1901>
I would think the pmod connector exists since I defined it in "connectors"
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<rjo>
plaes: ack. that looks correct.
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<zignig>
cr1901: having a look at your code... there is no pin 5 on pmod 0. user_led 0 is bound to nothing.
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<cr1901>
Oh you can't be serious... you actually have to map to the actual pin numbers on the connector?
<cr1901>
as opposed to 0, 1, 2, 3, 4, 5, etc...
<cr1901>
zignig: Yea I don't get this... how do I map user_led 0 to the fifth pin on the pmod2 connector?
<zignig>
hmmm , sorry my bad, it should map the ordinal of the pin from the connector.
<zignig>
however I'm not sure what it does with pins marked '-'
<cr1901>
zignig: They are counted
<zignig>
your platform , from platform.connectors in the console
<cr1901>
which means that pin "5" should become "7"